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    AHCT00

    Abstract: 74AHC00D 74AHC00 74AHC00BQ 74AHC00PW 74AHCT00 TSSOP14
    Text: 74AHC00; 74AHCT00 Quad 2-input NAND gate Rev. 04 — 28 April 2008 Product data sheet 1. General description The 74AHC00; 74AHCT00 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL LSTTL . It is specified in compliance with JEDEC


    Original     		PDF 74AHC00; 74AHCT00 74AHCT00 74AHC00: 74AHCT00: EIA/JESD22-A114E EIA/JESD22-A115-A AHCT00 74AHC00D 74AHC00 74AHC00BQ 74AHC00PW TSSOP14

    dhvqfn14 footprint

    Abstract: 74ALVC00 74ALVC00BQ 74ALVC00D 74ALVC00PW DHVQFN14 TSSOP14 sot762 footprint SOT762-1 AN01026
    Text: INTEGRATED CIRCUITS DATA SHEET 74ALVC00 Quad 2-input NAND gate Product specification Supersedes data of 2003 Feb 06 2003 May 14 Philips Semiconductors Product specification Quad 2-input NAND gate 74ALVC00 FEATURES DESCRIPTION • Wide supply voltage range from 1.65 to 3.6 V


    Original     		PDF 74ALVC00 74ALVC00 SCA75 613508/02/pp16 dhvqfn14 footprint 74ALVC00BQ 74ALVC00D 74ALVC00PW DHVQFN14 TSSOP14 sot762 footprint SOT762-1 AN01026

    Untitled

    Abstract: No abstract text available
    Text: 74LV00 Quad 2-input NAND gate Rev. 03 — 20 December 2007 Product data sheet 1. General description The 74LV00 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC00 and 74HCT00. The 74LV00 provides a quad 2-input NAND function.


    Original     		PDF 74LV00 74LV00 74HC00 74HCT00. JESD22-A114E JESD22-A115-A

    Untitled

    Abstract: No abstract text available
    Text: 74HC00; 74HCT00 Quad 2-input NAND gate Rev. 6 — 14 December 2011 Product data sheet 1. General description The 74HC00; 74HCT00 are high-speed Si-gate CMOS devices that comply with JEDEC standard no. 7A. They are pin compatible with Low-power Schottky TTL LSTTL .


    Original     		PDF 74HC00; 74HCT00 74HCT00 74HC00: 74HCT00: JESD22-A114F JESD22-A115-A

    74LVC00A

    Abstract: 74LVC00AD 74LVC00ADB 74LVC00APW
    Text: INTEGRATED CIRCUITS DATA SHEET 74LVC00A Quad 2-input NAND gate Product specification Supersedes data of 1998 Apr 28 2002 Mar 05 Philips Semiconductors Product specification Quad 2-input NAND gate 74LVC00A FEATURES DESCRIPTION • 5 V tolerant inputs for interfacing with 5 V logic


    Original     		PDF 74LVC00A 74LVC00A SCA74 613508/03/pp16 74LVC00AD 74LVC00ADB 74LVC00APW

    Untitled

    Abstract: No abstract text available
    Text: 74LVC132A-Q100 Quad 2-input NAND Schmitt trigger Rev. 1 — 4 April 2013 Product data sheet 1. General description The 74LVC132A-Q100 provides four 2-input NAND gates with Schmitt trigger inputs. It can transform slowly changing input signals into sharply defined, jitter-free output signals.


    Original     		PDF 74LVC132A-Q100 74LVC132A-Q100 74LVC132A

    Untitled

    Abstract: No abstract text available
    Text: 74LVC00A Quad 2-input NAND gate Rev. 7 — 25 April 2012 Product data sheet 1. General description The 74LVC00A provides four 2-input NAND gates. Schmitt trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these


    Original     		PDF 74LVC00A 74LVC00A JESD8-C/JESD36 JESD22-A114F

    Untitled

    Abstract: No abstract text available
    Text: 74HC03-Q100; 74HCT03-Q100 Quad 2-input NAND gate Rev. 1 — 4 July 2013 Product data sheet 1. General description The 74HC03-Q100; 74HCT03-Q100 is a quad 2-input NAND gate with open-drain outputs. Inputs include clamp diodes that enable the use of current limiting resistors to


    Original     		PDF 74HC03-Q100; 74HCT03-Q100 74HCT03-Q100 AEC-Q100 74HC03-Q100: 74HCT03-Q100:

    Untitled

    Abstract: No abstract text available
    Text: 74LVC132A Quad 2-input NAND Schmitt trigger Rev. 2 — 29 August 2011 Product data sheet 1. General description The 74LVC132A provides four 2-input NAND gates with Schmitt trigger inputs. It is capable of transforming slowly-changing input signals into sharply defined, jitter-free


    Original     		PDF 74LVC132A 74LVC132A

    IC 74HC00

    Abstract: No abstract text available
    Text: 74HC00-Q100; 74HCT00-Q100 Quad 2-input NAND gate Rev. 1 — 12 July 2012 Product data sheet 1. General description The 74HC00-Q100; 74HCT00-Q100 are high-speed Si-gate CMOS devices that comply with JEDEC standard no. 7A. They are pin compatible with Low-power Schottky TTL


    Original     		PDF 74HC00-Q100; 74HCT00-Q100 74HCT00-Q100 AEC-Q100 74HC00-Q100: IC 74HC00

    JESD22-C101E

    Abstract: No abstract text available
    Text: 74LVC00A Quad 2-input NAND gate Rev. 6 — 6 January 2012 Product data sheet 1. General description The 74LVC00A provides four 2-input NAND gates. Schmitt trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these


    Original     		PDF 74LVC00A 74LVC00A JESD8-C/JESD36 JESD22-C101E

    dhvqfn14

    Abstract: 74AHC00 74AHC00BQ 74AHC00D 74AHC00PW 74AHCT00 74AHCT00D 74AHCT00PW JESD22-A114E
    Text: 74AHC00; 74AHCT00 Quad 2-input NAND gate Rev. 03 — 8 January 2008 Product data sheet 1. General description The 74AHC00; 74AHCT00 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL LSTTL . They are specified in compliance with JEDEC


    Original     		PDF 74AHC00; 74AHCT00 74AHCT00 74AHC00 JESD22-A114E JESD22-A115-A dhvqfn14 74AHC00BQ 74AHC00D 74AHC00PW 74AHCT00D 74AHCT00PW

    74AHC00D

    Abstract: 74AHC00 74AHC00PW 74AHCT00 74AHCT00D
    Text: INTEGRATED CIRCUITS DATA SHEET 74AHC00; 74AHCT00 Quad 2-input NAND gate Product specification Supersedes data of 1998 Dec 09 File under Integrated Circuits, IC06 1999 Sep 23 Philips Semiconductors Product specification Quad 2-input NAND gate FEATURES • ESD protection:


    Original     		PDF 74AHC00; 74AHCT00 EIA/JESD22-A114-A EIA/JESD22-A115-A EIA/JESD22-C101 545002/02/pp16 74AHC00D 74AHC00 74AHC00PW 74AHCT00 74AHCT00D

    74LVC00A

    Abstract: 74LVC00ABQ 74LVC00AD 74LVC00ADB 74LVC00APW DHVQFN14 SSOP14 TSSOP14 dhvqfn14 footprint
    Text: INTEGRATED CIRCUITS DATA SHEET 74LVC00A Quad 2-input NAND gate Product specification Supersedes data of 2002 Mar 05 2003 May 07 Philips Semiconductors Product specification Quad 2-input NAND gate 74LVC00A FEATURES DESCRIPTION • 5 V tolerant inputs for interfacing with 5 V logic


    Original     		PDF 74LVC00A 74LVC00A SCA75 613508/04/pp20 74LVC00ABQ 74LVC00AD 74LVC00ADB 74LVC00APW DHVQFN14 SSOP14 TSSOP14 dhvqfn14 footprint

    Untitled

    Abstract: No abstract text available
    Text: 74LVC132A Quad 2-input NAND Schmitt trigger Rev. 3 — 7 December 2011 Product data sheet 1. General description The 74LVC132A provides four 2-input NAND gates with Schmitt trigger inputs. It is capable of transforming slowly-changing input signals into sharply defined, jitter-free


    Original     		PDF 74LVC132A 74LVC132A

    74HCT00

    Abstract: 74HC00 74HC00 ordering information 74HCT00D CI 74HC00 74HC00 quad CMOS nand gate TTL 74HC00 74HC00 NOT GATE 74HC00BQ
    Text: 74HC00-Q100; 74HCT00-Q100 Quad 2-input NAND gate Rev. 1 — 12 July 2012 Product data sheet 1. General description The 74HC00-Q100; 74HCT00-Q100 are high-speed Si-gate CMOS devices that comply with JEDEC standard no. 7A. They are pin compatible with Low-power Schottky TTL


    Original     		PDF 74HC00-Q100; 74HCT00-Q100 74HCT00-Q100 AEC-Q100 74HC00-Q100: 74HCT00-Q100: protectio13 74HCT00 74HC00 74HC00 ordering information 74HCT00D CI 74HC00 74HC00 quad CMOS nand gate TTL 74HC00 74HC00 NOT GATE 74HC00BQ

    74LVC00A

    Abstract: 74LVC00ABQ 74LVC00AD 74LVC00ADB 74LVC00APW SSOP14 TSSOP14
    Text: INTEGRATED CIRCUITS DATA SHEET 74LVC00A Quad 2-input NAND gate Product specification Supersedes data of 2003 May 07 2003 Sep 04 Philips Semiconductors Product specification Quad 2-input NAND gate 74LVC00A FEATURES DESCRIPTION • 5 V tolerant inputs for interfacing with 5 V logic


    Original     		PDF 74LVC00A 74LVC00A SCA75 R20/05/pp15 74LVC00ABQ 74LVC00AD 74LVC00ADB 74LVC00APW SSOP14 TSSOP14

    74hc00n

    Abstract: 74hct00 CI 74hct00 74HC00DB 74HC00PW 74HC00 14 pin 74HC00 74HC00 B1 74HC00 ordering information 74HCT00DB
    Text: 74HC00; 74HCT00 Quad 2-input NAND gate Rev. 6 — 14 December 2011 Product data sheet 1. General description The 74HC00; 74HCT00 are high-speed Si-gate CMOS devices that comply with JEDEC standard no. 7A. They are pin compatible with Low-power Schottky TTL LSTTL .


    Original     		PDF 74HC00; 74HCT00 74HCT00 74HC00: 74HCT00: JESD22-A114F JESD22-A115-A 74hc00n CI 74hct00 74HC00DB 74HC00PW 74HC00 14 pin 74HC00 74HC00 B1 74HC00 ordering information 74HCT00DB

    Untitled

    Abstract: No abstract text available
    Text: 74HC03; 74HCT03 Quad 2-input NAND gate Rev. 3 — 27 June 2013 Product data sheet 1. General description The 74HC03; 74HCT03 is a quad 2-input NAND gate with open-drain outputs. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to


    Original     		PDF 74HC03; 74HCT03 74HCT03 74HC03: 74HCT03: JESD22-A114F JESD22-A115-A 74HC03N HCT03

    Untitled

    Abstract: No abstract text available
    Text: INTEGRATED CIRCUITS DAT 74ALVC00 Quad 2-input NAND gate Product specification Supersedes data of 2003 Feb 06 2003 May 14 Philips Semiconductors Product specification Quad 2-input NAND gate 74ALVC00 FEATURES DESCRIPTION • Wide supply voltage range from 1.65 to 3.6 V


    Original     		PDF 74ALVC00 74ALVC00 SCA75 613508/02/pp16

    Untitled

    Abstract: No abstract text available
    Text: INTEGRATED CIRCUITS DATA SHEET 74ALVC00 Quad 2-input NAND gate Preliminary specification File under Integrated Circuits, IC24 2002 Apr 16 Philips Semiconductors Preliminary specification Quad 2-input NAND gate 74ALVC00 FEATURES DESCRIPTION • Wide supply voltage range of 1.65 to 3.6 V


    Original     		PDF 74ALVC00 JESD8B/JESD36

    Untitled

    Abstract: No abstract text available
    Text: INTEGRATED CIRCUITS DATA SHEET 74ALVC00 Quad 2-input NAND gate Product specification Supersedes data of 2003 Feb 06 2003 Mar 25 Philips Semiconductors Product specification Quad 2-input NAND gate 74ALVC00 FEATURES DESCRIPTION • Wide supply voltage range from 1.65 to 3.6 V


    Original     		PDF 74ALVC00 JESD8B/JESD36 EIA/JESD22-A114-A EIA/JESD22-A115-A

    Untitled

    Abstract: No abstract text available
    Text: 74LVC00A-Q100 Quad 2-input NAND gate Rev. 1 — 27 February 2013 Product data sheet 1. General description The 74LVC00A-Q100 provides four 2-input NAND gates. Schmitt trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.


    Original     		PDF 74LVC00A-Q100 74LVC00A-Q100 AEC-Q100

    74LVC132A

    Abstract: 74LVC132ABQ 74LVC132AD 74LVC132APW TSSOP14
    Text: 74LVC132A Quad 2-input NAND Schmitt trigger Rev. 01 — 15 December 2006 Product data sheet 1. General description The 74LVC132A is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. The 74LVC132A provides four 2-input NAND gates with Schmitt trigger inputs. It is


    Original     		PDF 74LVC132A 74LVC132A 74LVC132ABQ 74LVC132AD 74LVC132APW TSSOP14