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    MIPS RM5231 Search Results

    MIPS RM5231 Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    TMS320C28344ZFET Texas Instruments Delfino™ 32-bit MCU with 300 MIPS, FPU, 260 KB RAM, EMIF 256-BGA -40 to 105 Visit Texas Instruments
    TMS320C28346ZFEQ Texas Instruments Delfino™ 32-bit MCU with 300 MIPS, FPU, 516 KB RAM, EMIF 256-BGA -40 to 125 Visit Texas Instruments Buy
    TMS320C28342ZFET Texas Instruments Delfino™ 32-bit MCU with 300 MIPS, FPU, 196 KB RAM, EMIF 256-BGA -40 to 105 Visit Texas Instruments Buy
    TMS320C28343ZFEQ Texas Instruments Delfino™ 32-bit MCU with 200 MIPS, FPU, 260 KB RAM, EMIF 256-BGA -40 to 125 Visit Texas Instruments Buy
    TMS320C28346ZFETR Texas Instruments Delfino™ 32-bit MCU with 300 MIPS, FPU, 516 KB RAM, EMIF 256-BGA -40 to 105 Visit Texas Instruments

    MIPS RM5231 Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    Rm7035c

    Abstract: No abstract text available
    Text: CM5470 Preliminary GEN-M7K-56-000 Data Sheet PM A MEMBER OF PMC-SIERRA’S CLOCK FAMILY 8: 03 System Clock Generator For MIPS-Based Designs 04 03 :4 PMC-Sierra’s GEN-M7K-56-000 is perfectly tailored to perform the clock generation required in a design using MIPS-basedTM processors. The GEN-M7K-56-000 covers the clocking needs of the 5K and


    Original     		PDF CM5470 GEN-M7K-56-000 RM5231A, RM5261A, RM7000A, RM7000B, RM7000C, RM7035C, Rm7035c

    Untitled

    Abstract: No abstract text available
    Text: CM5470 Preliminary GEN-M7K-56-000 Data Sheet AM A MEMBER OF PMC-SIERRA’S CLOCK FAMILY 1: 57 System Clock Generator For MIPS-Based Designs 04 03 :4 PMC-Sierra’s GEN-M7K-56-000 is perfectly tailored to perform the clock generation required in a design using MIPS-basedTM processors. The GEN-M7K-56-000 covers the clocking needs of the 5K and


    Original     		PDF CM5470 GEN-M7K-56-000 RM5231A, RM5261A, RM7000A, RM7000B, RM7000C, RM7035C,

    rm7035c

    Abstract: MIPS RM7965 CM5470
    Text: CM5470 Preliminary GEN-M7K-56-000 Data Sheet PM A MEMBER OF PMC-SIERRA’S CLOCK FAMILY 1: 59 System Clock Generator For MIPS-Based Designs 00 5 10 :1 PMC-Sierra’s GEN-M7K-56-000 is perfectly tailored to perform the clock generation required in a design using MIPS-basedTM processors. The GEN-M7K-56-000 covers the clocking needs of the 5K and


    Original     		PDF CM5470 GEN-M7K-56-000 RM5231A, RM5261A, RM7000A, RM7000B, RM7000C, RM7035C, rm7035c MIPS RM7965

    RM7035C

    Abstract: No abstract text available
    Text: CM5470 Preliminary GEN-M7K-56-000 Data Sheet AM A MEMBER OF PMC-SIERRA’S CLOCK FAMILY 2: 24 System Clock Generator For MIPS-Based Designs 04 09 :1 PMC-Sierra’s GEN-M7K-56-000 is perfectly tailored to perform the clock generation required in a design using MIPS-basedTM processors. The GEN-M7K-56-000 covers the clocking needs of the 5K and


    Original     		PDF CM5470 GEN-M7K-56-000 RM5231A, RM5261A, RM7000A, RM7000B, RM7000C, RM7035C, RM7035C

    rm7065c

    Abstract: No abstract text available
    Text: CM5470 Preliminary GEN-M7K-56-000 Data Sheet AM A MEMBER OF PMC-SIERRA’S CLOCK FAMILY 0: 50 System Clock Generator For MIPS-Based Designs 5 02 :2 PMC-Sierra’s GEN-M7K-56-000 is perfectly tailored to perform the clock generation required in a design using MIPS-basedTM processors. The GEN-M7K-56-000 covers the clocking needs of the 5K and


    Original     		PDF CM5470 GEN-M7K-56-000 RM5231A, RM5261A, RM7000A, RM7000B, RM7000C, RM7035C, rm7065c

    Rm7035c

    Abstract: No abstract text available
    Text: CM5470 Preliminary GEN-M7K-56-000 Data Sheet AM A MEMBER OF PMC-SIERRA’S CLOCK FAMILY 7: 56 System Clock Generator For MIPS-Based Designs 04 11 :1 PMC-Sierra’s GEN-M7K-56-000 is perfectly tailored to perform the clock generation required in a design using MIPS-basedTM processors. The GEN-M7K-56-000 covers the clocking needs of the 5K and


    Original     		PDF CM5470 GEN-M7K-56-000 RM5231A, RM5261A, RM7000A, RM7000B, RM7000C, RM7035C, Rm7035c

    Untitled

    Abstract: No abstract text available
    Text: CM5470 Preliminary GEN-M7K-56-000 Data Sheet AM A MEMBER OF PMC-SIERRA’S CLOCK FAMILY 9: 42 System Clock Generator For MIPS-Based Designs 5 09 :5 PMC-Sierra’s GEN-M7K-56-000 is perfectly tailored to perform the clock generation required in a design using MIPS-basedTM processors. The GEN-M7K-56-000 covers the clocking needs of the 5K and


    Original     		PDF CM5470 GEN-M7K-56-000 RM5231A, RM5261A, RM7000A, RM7000B, RM7000C, RM7035C,

    Untitled

    Abstract: No abstract text available
    Text: RM5231 Microprocessor with 32-Bit System Bus Document Rev. 1.3 Date: 01/2000 FEATURES • Dual Issue superscalar microprocessor — 150, 200, & 250 MHz operating frequencies — 300 Dhrystone2.1 MIPS • System interface optimized for embedded applications


    Original     		PDF RM5231â 32-Bit RM5231-DS0011300001 RM5231

    MIPS RM5231

    Abstract: RM5231-150Q R4000 R4650 R4700 R5000 RM5231
    Text: RM5231 Superscalar Microprocessor with 64-Bit System Bus FEATURES • Dual Issue superscalar microprocessor — 150, 200, 225, & 250 MHz operating frequencies — 300 Dhrystone2.1 MIPS — SPECInt95 5.0, SPECfp95 5.25 • System interface optimized for embedded applications


    Original     		PDF RM5231TM 64-Bit SPECInt95 SPECfp95 32-bit RM5231-DS0011209910 MIPS RM5231 RM5231-150Q R4000 R4650 R4700 R5000 RM5231

    GT-64240

    Abstract: gt64240 ieee 32 bit floating point multiplier IT8172 RM5261A RM5231A RM7035C RM7065C EV-64120A it8172g
    Text: RM5231A/RM5261A Microprocessors Released 64-Bit MIPS RISC Microprocessors with 32/64-bit System Bus FEATURES Virtually indexed, physically tagged. Write-back and write-through on per-page basis. • Pipeline restart on first double word for data cache misses.


    Original     		PDF RM5231A/RM5261A 64-Bit 32/64-bit 64/32/16/8-bit 64/32-bit PMC-2010740 GT-64240 gt64240 ieee 32 bit floating point multiplier IT8172 RM5261A RM5231A RM7035C RM7065C EV-64120A it8172g

    5261A

    Abstract: MIPS 32-bit bus architecture ieee 32 bit floating point multiplier GALILEO TECHNOLOGY 32-bit microprocessor pipeline architecture V340HPC Marvell IEEE754 RM5231A RM5261A
    Text: RM5231A/5261A 64-Bit MIPS RISC Microprocessor with 32/64-Bit System Bus FEATURES • Dual-Issue 64-bit Superscalar architecture • High-performance 64-bit integer unit • High-throughput fully pipelined 64bit floating point unit IEEE754 • High performance SysAD interface


    Original     		PDF RM5231A/5261A 64-Bit 32/64-Bit 64bit IEEE754) 32-bit 5261A MIPS 32-bit bus architecture ieee 32 bit floating point multiplier GALILEO TECHNOLOGY 32-bit microprocessor pipeline architecture V340HPC Marvell IEEE754 RM5231A RM5261A

    hurricane

    Abstract: V320USC EVALUATION KIT HR52312003220 pci slot pcb layout MH64BT0330011 RM5231 V320USC pci card schematic V320USC-75LP
    Text: Hurricane V320USC EVALUATION KIT with the QED RM5231 MIPS® Processor Features the V320USC PCI System Controller for 32-bit PCI Bus, designed by V3 Semiconductor Supports QED® RM5230™ and RM5231™ processors Fully compliant with PCI Local Bus Specification, Revision 2.2


    Original     		PDF V320USC RM5231TM 32-bit RM5230TM 10-pin TB-HR01-0200 hurricane V320USC EVALUATION KIT HR52312003220 pci slot pcb layout MH64BT0330011 RM5231 pci card schematic V320USC-75LP

    V320USC

    Abstract: HR52312003220 HT77291333212 RM5231 SH7729
    Text: V320USC HIGH INTEGRATION, LOW COST PCI SYSTEM CONTROLLER For 32-bit MIPS and SuperH Processors Fully compliant with PCI Local Bus Specification, Revision 2.2 Configurable for system master, PCI bus master, or PCI target operation SDRAM Controller with support


    Original     		PDF V320USC 32-bit 2348G TB-UC01-0200 V320USC HR52312003220 HT77291333212 RM5231 SH7729

    RM7065C

    Abstract: RM7035C exposed tektronix 466 RM5231A RM5261A RM7065 RM7065A gt-64240 GT64240
    Text: RM7035C/RM7065C Microprocessors Preliminary 64-Bit MIPS RISC Microprocessors with Integrated L2 Cache FEATURES 16 Kbytes instruction, 16 Kbytes data, 256 Kbytes on-chip secondary. • Per line cache locking in primaries and secondary. • Fast Packet Cache increases


    Original     		PDF RM7035C/RM7065C 64-Bit PMC-2020578 RM7065C RM7035C exposed tektronix 466 RM5231A RM5261A RM7065 RM7065A gt-64240 GT64240

    ACT5231

    Abstract: ACT-5231PC-133F22C R4700 R5000 RM5231
    Text: ACT5231 32-Bit Superscaler Microprocessor Features • Full militarized QED RM5231 microprocessor ■ Pinout compatible with popular RM5230 with split power sup plies 2.5V and 3.3V ■ Dual Issue superscalar microprocessor - can issue one integer and one floating-point instruction per cycle


    Original     		PDF ACT5231 32-Bit RM5231 RM5230 SPECInt95 SPECfp95 MIL-PRF-38534 150MHz 200MHz ACT5231 ACT-5231PC-133F22C R4700 R5000

    RM5231

    Abstract: MS-022 R4000 RM5200 ALU of 4 bit adder and subtractor by917
    Text: RM5231 Microprocessor with 32-Bit System Bus Data Sheet Released RM5231 RM5231™ Microprocessor with 32-Bit System Bus Data Sheet Proprietary and Confidential Issue 1, March 2001 Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use


    Original     		PDF RM5231TM 32-Bit RM5231 32-Bit PMC-2002165, PMC-2002165 RM5231 MS-022 R4000 RM5200 ALU of 4 bit adder and subtractor by917

    R4000

    Abstract: RM5200 RM5231A
    Text: RM5231A Microprocessor with 32-Bit System Bus Data Sheet Preliminary RM5231A RM5231A™ Microprocessor with 32-Bit System Bus Data Sheet Proprietary and Confidential Preliminary Issue 3, February 2002 Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use


    Original     		PDF RM5231ATM 32-Bit RM5231A 32-Bit PMC-2002174, PMC-2002174 R4000 RM5200 RM5231A

    MS-022

    Abstract: R4000 RM5200 RM5231
    Text: 06 :14 :26 AM RM5231 Microprocessor with 32-Bit System Bus Data Sheet Released on Th ur sd ay ,0 8A ug us t, 20 02 RM5231 Data Sheet Proprietary and Confidential Do wn loa de db yt am er na bil of Si lic on Ex pe rt RM5231™ Microprocessor with 32-Bit


    Original     		PDF RM5231TM 32-Bit RM5231 32-Bit PMC-2002165, MS-022 R4000 RM5200 RM5231

    R4000

    Abstract: RM5200 RM5231A stream register cache coherency RM5231A-250H
    Text: RM5231A Microprocessor with 32-Bit System Bus Data Sheet Preliminary RM5231A RM5231A™ Microprocessor with 32-Bit System Bus Data Sheet Proprietary and Confidential Preliminary Issue 1, March 2001 Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use


    Original     		PDF RM5231ATM 32-Bit RM5231A 32-Bit PMC-2002174, PMC-2002174 R4000 RM5200 RM5231A stream register cache coherency RM5231A-250H

    block diagram i3 processor

    Abstract: implementing ALU with adder/subtractor pin diagram i3 processor R4000 MICROPROCESSOR R4000 RM5200 RM5231A
    Text: RM5231A Microprocessor with 32-Bit System Bus Data Sheet Preliminary RM5231A RM5231A™ Microprocessor with 32-Bit System Bus Data Sheet Proprietary and Confidential Preliminary Issue 2, September 2001 Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use


    Original     		PDF RM5231ATM 32-Bit RM5231A 32-Bit PMC-2002174, PMC-2002174 block diagram i3 processor implementing ALU with adder/subtractor pin diagram i3 processor R4000 MICROPROCESSOR R4000 RM5200 RM5231A

    Untitled

    Abstract: No abstract text available
    Text: :4 5: 23 AM RM5231A Microprocessor with 32-Bit System Bus Data Sheet Released es da y, 14 Se pt em be r, 20 04 06 RM5231A Data Sheet Proprietary and Confidential Released Issue 4, February 2004 Do wn lo ad ed by Co nt e nt Te a m of P ar tm in er In co


    Original     		PDF RM5231ATM 32-Bit PMC-2002174, RM5231A

    LIC AGENTS DATA

    Abstract: RM5231A R4000 RM5200 lic policy
    Text: :15 :32 AM RM5231A Microprocessor with 32-Bit System Bus Data Sheet Preliminary Th ur sd ay ,0 8A ug us t, 2 00 2 06 RM5231A Data Sheet Proprietary and Confidential Preliminary Issue 3, February 2002 Do wn loa de db yt am er na bil of Si lic on Ex pe rt


    Original     		PDF RM5231ATM 32-Bit RM5231A 32-Bit PMC-2002174, RM5231A LIC AGENTS DATA R4000 RM5200 lic policy

    Untitled

    Abstract: No abstract text available
    Text: 07 :2 1: 44 P M RM5231A Microprocessor with 32-Bit System Bus Data Sheet Released co n Tu es da y, 24 Ja nu ar y, 20 12 RM5231A Data Sheet Proprietary and Confidential Released Issue 4, February 2004 Do wn lo a de d [c on tro lle d] by Co n te nt Te am


    Original     		PDF RM5231Aâ 32-Bit RM5231A 32-Bit PMC-2002174,

    5650300

    Abstract: XXXW
    Text: QED RISCMark RM5231™ 64-Bit Superscalar Microprocessor FEATURES: • Pinout com p atib le w ith po pu lar R M 5230 w ith split po w e r s u p ­ plies 2.5V and 3.3V • Dual Issue su p e rsca la r m icro p ro ce sso r - can issue one integer and one floa ting -point in stru ction pe r cycle


    OCR Scan     		PDF RM5231TM 64-Bit DS-5231, 5650300 XXXW