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    SD6000 dual fet

    Abstract: SD6000 SD6000v SD6000-V
    Text: SD6000-V G EN ER A L FEATURES • • • • • PIN CO N FIG U RA TIO N Positive bias only Low gate voltages Enhancement mode operation Zener diode gate protection Ion implanted for greater reliability V PACKAGE G ate N o . 2 M ix e r FEATU RES RF AM P Section


    OCR Scan     		PDF SD6000-V 100MHz 025pF 15mmhos 5-20pF SD6000 dual fet SD6000 SD6000v SD6000-V

    78M05CDB

    Abstract: 78M05 ST transistor 78M12C S500mA 78M08C ST 78m05 78M12C 78M05DB S200M 78M08CU
    Text: FEATURES ABSOLUTE MAXIMUM RATINGS • OUTPUT CURRENT UP TO 500MA • NO EXTERNAL COMPONENTS • INTERNAL THERMAL OVERLOAD PRO­ TECTION • INTERNAL SHORT CIRCUIT CURRENT LIMITING • OUTPUT TRANSISTOR SAFE-AREA COMPENSATION • AVAILABLE IN THE TO-220 AND THE


    OCR Scan     		PDF 500MA O-220 78M00 78M00C T0-220 MIAI06 78M05CDB 78M05 ST transistor 78M12C S500mA 78M08C ST 78m05 78M12C 78M05DB S200M 78M08CU