D52A
Abstract: No abstract text available
Text: DP8402A,DP8403,DP8404,DP8405 DP8402A/DP8403/DP8404/DP8405 32-Bit Parallel Error Detection and Correction Circuits EDAC's Literature Number: SNOSBX3A August 1989 DP8402A DP8403 DP8404 DP8405 32-Bit Parallel Error Detection and Correction Circuits (EDAC’s)
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DP8402A
DP8403
DP8404
DP8405
DP8402A/DP8403/DP8404/DP8405
32-Bit
DP8405
D52A
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HI-6121
Abstract: No abstract text available
Text: HI-6120 Parallel Bus Interface and HI-6121 Serial Peripheral Interface SPI MIL-STD-1553 Remote Terminal ICs GENERAL DESCRIPTION “RoHS compliant” lead-free option is offered. REMOTE TERMINAL FEATURES • Fully integrated 3.3V Remote Terminal meets all
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HI-6120
HI-6121
MIL-STD-1553
16-bit
100-pin
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HI-6120
Abstract: Holt 1553 Controller - HI6110 HI-6121 HOLT INC 00FF motorola mc17 MIL-STD1760 6121 HOLT
Text: November 2009 HI-6120 Parallel Bus Interface and HI-6121 Serial Peripheral Interface SPI MIL-STD-1553 Remote Terminal ICs GENERAL DESCRIPTION REMOTE TERMINAL FEATURES The HI-6120 and HI-6121 provide a complete, integrated, 3.3V MIL-STD-1553 Remote Terminal in a monolithic
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HI-6120
HI-6121
MIL-STD-1553
16-bit
100-pin
Holt 1553 Controller - HI6110
HOLT INC
00FF
motorola mc17
MIL-STD1760
6121 HOLT
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HI6120P
Abstract: No abstract text available
Text: HI-6120 Parallel Bus Interface and HI-6121 Serial Peripheral Interface SPI MIL-STD-1553 Remote Terminal ICs GENERAL DESCRIPTION The HI-6120 and HI-6121 provide a complete, integrated, 3.3V MIL-STD-1553 Remote Terminal in a monolithic silicon gate CMOS device. Two host interface options are
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HI-6120
HI-6121
MIL-STD-1553
MIL-STD-1553B
16-bit
100-pin
HI6120P
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HI-6121
Abstract: hi6121
Text: FEATURES The HI-6120 and HI-6121 provide a complete, integrated, 3.3V MIL-STD-1553 Remote Terminal in a monolithic silicon gate CMOS device. Two host interface options are offered: The HI-6120 uses a 16-bit parallel host bus interface for access to registers and RAM and is offered in a
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HI-6120
HI-6121
MIL-STD-1553
16-bit
100-pin
hi6121
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PM-DB2776
Abstract: hi6121 35BUSA transformer coupling mil-std1553 PM-DB2762
Text: FEATURES The HI-6120 and HI-6121 provide a complete, integrated, 3.3V MIL-STD-1553 Remote Terminal in a monolithic silicon gate CMOS device. Two host interface options are offered: The HI-6120 uses a 16-bit parallel host bus interface for access to registers and RAM and is offered in a
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HI-6120
HI-6121
MIL-STD-1553
16-bit
100-pin
PM-DB2776
hi6121
35BUSA
transformer coupling mil-std1553
PM-DB2762
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Untitled
Abstract: No abstract text available
Text: FEATURES The HI-6120 and HI-6121 provide a complete, integrated, 3.3V MIL-STD-1553 Remote Terminal in a monolithic silicon gate CMOS device. Two host interface options are offered: The HI-6120 uses a 16-bit parallel host bus interface for access to registers and RAM and is offered in a
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HI-6120
HI-6121
MIL-STD-1553
16-bit
100-pin
52-pin
64-pin
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HI-6110
Abstract: Holt 1553 Controller HI6110 HOLT INC Holt 1553 Controller - HI6110 HI-6121 HI-6120 hi6121 0x0043 DS6120 MIL-STD-1553B
Text: FEATURES The HI-6120 and HI-6121 provide a complete, integrated, 3.3V MIL-STD-1553 Remote Terminal in a monolithic silicon gate CMOS device. Two host interface options are offered: The HI-6120 uses a 16-bit parallel host bus interface for access to registers and RAM and is offered in a
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HI-6120
HI-6121
MIL-STD-1553
16-bit
100-pin
52-pin
64-pin
HI-6110
Holt 1553 Controller HI6110
HOLT INC
Holt 1553 Controller - HI6110
hi6121
0x0043
DS6120
MIL-STD-1553B
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Untitled
Abstract: No abstract text available
Text: FEATURES The HI-6120 and HI-6121 provide a complete, integrated, 3.3V MIL-STD-1553 Remote Terminal in a monolithic silicon gate CMOS device. Two host interface options are offered: The HI-6120 uses a 16-bit parallel host bus interface for access to registers and RAM and is offered in a
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HI-6120
HI-6121
MIL-STD-1553
16-bit
100-pin
52-pin
64-pin
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Untitled
Abstract: No abstract text available
Text: FEATURES The HI-6120 and HI-6121 provide a complete, integrated, 3.3V MIL-STD-1553 Remote Terminal in a monolithic silicon gate CMOS device. Two host interface options are offered: The HI-6120 uses a 16-bit parallel host bus interface for access to registers and RAM and is offered in a
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HI-6120
HI-6121
MIL-STD-1553
16-bit
100-pin
52-pin
64-pin
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Untitled
Abstract: No abstract text available
Text: HI-6130 / HI-6131 MIL-STD-1553 / MIL-STD-1760 3.3V BC / MT / RT Multi-Terminal Device GENERAL DESCPIPTION • Two options are offered for host access to internal registers and static RAM: The HI-6130 uses a 16-bit parallel bus; the HI-6131 communicates with the host
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HI-6130
HI-6131
MIL-STD-1553
MIL-STD-1760
16-bit
HI-6131
HI-6130
16-bit
100-pin
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IRIG B generator
Abstract: lm 16151 HI-6131 HI-6130 DS6130 pin diagram for IC 1619 30 pin HI-6132 TT32 digital timer IRIG B 122 generator 0x02FE
Text: HI-6130 / HI-6131 / HI-6132 MIL-STD-1553 / MIL-STD-1760 3.3V BC / MT / RT Multi-Terminal Device GENERAL DESCPIPTION • The 3.3V CMOS HI-613x device provides a complete single- or multi-function interface between a host processor and MIL-STD-1553B bus. Each IC contains
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HI-6130
HI-6131
HI-6132
MIL-STD-1553
MIL-STD-1760
16-bit
48bit
IRIG106
IRIG-106
IRIG B generator
lm 16151
DS6130
pin diagram for IC 1619 30 pin
TT32 digital timer
IRIG B 122 generator
0x02FE
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Untitled
Abstract: No abstract text available
Text: HI-6130 / HI-6131 MIL-STD-1553 / MIL-STD-1760 3.3V BC / MT / RT Multi-Terminal Device GENERAL DESCPIPTION • Two options are offered for host access to internal registers and static RAM: The HI-6130 uses a 16-bit parallel bus; the HI-6131 communicates with the host
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HI-6130
HI-6131
MIL-STD-1553
MIL-STD-1760
16-bit
HI-6131
HI-6130
16-bit
100-pin
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Untitled
Abstract: No abstract text available
Text: HI-6130 / HI-6131 / HI-6132 MIL-STD-1553 / MIL-STD-1760 3.3V BC / MT / RT Multi-Terminal Device GENERAL DESCPIPTION • The 3.3V CMOS HI-613x device provides a complete single- or multi-function interface between a host processor and MIL-STD-1553B bus. Each IC contains
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HI-6130
HI-6131
HI-6132
MIL-STD-1553
MIL-STD-1760
HI-613x
MIL-STD-1553B
HI-6130,
HI-6131
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Untitled
Abstract: No abstract text available
Text: HI-6130 / HI-6131 / HI-6132 MIL-STD-1553 / MIL-STD-1760 3.3V BC / MT / RT Multi-Terminal Device GENERAL DESCPIPTION • The 3.3V CMOS HI-613x device provides a complete single- or multi-function interface between a host processor and MIL-STD-1553B bus. Each IC contains
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HI-6130
HI-6131
HI-6132
MIL-STD-1553
MIL-STD-1760
HI-613x
MIL-STD-1553B
HI-6130,
HI-6131
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IRIG B generator
Abstract: HI-6131 IRIG B 122 generator lm 16151 IRIG-106 BT 2323 M ic pin configuration 80HEX Holt 1553 Controller HI6110 mc16 TSR16
Text: HI-6130 / HI-6131 / HI-6132 MIL-STD-1553 / MIL-STD-1760 3.3V BC / MT / RT Multi-Terminal Device GENERAL DESCPIPTION • The 3.3V CMOS HI-613x device provides a complete single- or multi-function interface between a host processor and MIL-STD-1553B bus. Each IC contains
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HI-6130
HI-6131
HI-6132
MIL-STD-1553
MIL-STD-1760
16-bit
48bit
IRIG106
IRIG-106
IRIG B generator
IRIG B 122 generator
lm 16151
BT 2323 M ic pin configuration
80HEX
Holt 1553 Controller HI6110
mc16
TSR16
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Untitled
Abstract: No abstract text available
Text: HI-6130 / HI-6131 / HI-6132 MIL-STD-1553 / MIL-STD-1760 3.3V BC / MT / RT Multi-Terminal Device GENERAL DESCPIPTION • The 3.3V CMOS HI-613x device provides a complete single- or multi-function interface between a host processor and MIL-STD-1553B bus. Each IC contains
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HI-6130
HI-6131
HI-6132
MIL-STD-1553
MIL-STD-1760
HI-613x
MIL-STD-1553B
HI-6132:
121BGA
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Untitled
Abstract: No abstract text available
Text: HI-6130 / HI-6131 / HI-6132 MIL-STD-1553 / MIL-STD-1760 3.3V BC / MT / RT Multi-Terminal Device GENERAL DESCPIPTION • The 3.3V CMOS HI-613x device provides a complete single- or multi-function interface between a host processor and MIL-STD-1553B bus. Each IC contains
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HI-6130
HI-6131
HI-6132
MIL-STD-1553
MIL-STD-1760
HI-613x
MIL-STD-1553B
HI-6130,
HI-6131
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79R3020
Abstract: 7 bit hamming code practical application of parity generator 49C466 R3000 processor error monitor comparator multiplexer parity error multiplexer parity comparator IDT49C466 49C465 R3000
Text: ERROR DETECTION AND CORRECTION WITH IDT49C466 APPLICATION NOTE AN-94 APPLICATION NOTE AN-94 ERROR DETECTION AND CORRECTION WITH IDT49C466 Integrated Device Technology, Inc. By Anupama Hegde INTRODUCTION ERROR DETECTION AND CORRECTION WITH It is widely accepted that system failures and down time THE 49C466
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IDT49C466
AN-94
49C466
79R3020
7 bit hamming code
practical application of parity generator
49C466
R3000 processor
error monitor comparator multiplexer parity
error multiplexer parity comparator
IDT49C466
49C465
R3000
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MDX-L
Abstract: M020 m043 M062 MD10 MD14 MD22 AS6364
Text: 64-BIT FLOW-THRU ERROR DETECTION AND CORRECTIONORCINT _D 33121 FEBRUARY 1 9 9 0 -R E V IS E D S EP TE M B E R 1990 12-ns Max Pass-Thru Operation When Used in Correct-Only-On-Error Configurations 17 X 17 GA PACKAGE {TOP VIEW 8 Detects and Corrects Single-Bit Errors
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64-BIT
D3312,
1990-REVISED
12-ns
48-mA
SN74AS6364
ALS6301
MDX-L
M020
m043
M062
MD10
MD14
MD22
AS6364
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LR3000
Abstract: LR3000A
Text: Chapter 3 LR3202A L-Bus Controller This chapter describes the LR3202A L-Bus Controller. Chapter 3 is organized into these sections: • General Description ■ Configuring the LR3202A ■ Programming the System Control Registers ■ Signal Definitions ■ L-Bus Operation
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LR3202A
LR3202A
LR3000
LR3000A
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EK117
Abstract: EK119 23d14 sun SPARC 50 EL B17 D126D P3020
Text: STP3020 SPA RC T echrdogy Business Novem ber 1994 ST P 3020 DATA SHEET D System Memory Controller escription The STP3020 System Memory controller SMC interfaces to an array of DRAM and VRAM SIMMs. It accelerates graphics and imaging to main memory and frame buffers. It also provides the interface for
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STP3020
STP3020
STP3021
STP3022
STB3DS154-894
EK117
EK119
23d14
sun SPARC 50
EL B17
D126D
P3020
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k535
Abstract: CDB22 LR3000 cxl tuner diagram interfacing of memory devices with 8086 LB1K LR3202A LR3203 LR3205 LR32D04
Text: Chapter 3 LR3202A L-Bus Controller This chapter describes the LR3202A L-Bus Controller. Chapter 3 is organized into these sections: • General Description ■ Configuring the LR3202A ■ Programming the System Control Registers ■ Signal Definitions ■ L-Bus Operation
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LR3202A
LR3202A
k535
CDB22
LR3000
cxl tuner diagram
interfacing of memory devices with 8086
LB1K
LR3203
LR3205
LR32D04
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str f 6167
Abstract: amz8127 str 6167 supi 3 ls z80b Am8001 AM8163 IC HS 8167 z80 multibus 74LS240
Text: Am8163/Am8167 A m 8 1 6 3 /A m 8 1 6 7 Dynamic Memory Timing, Refresh and EDC Controllers DISTINCTIVE CHARACTERISTICS EDC error flag latches for error logging under software control Two timing configurations support a broad range of processors Z80, Z8000, 8086, 8088, MC68000
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Am8163/Am8167
Z8000,
MC68000)
Am8163
Am8167
1553A
str f 6167
amz8127
str 6167
supi 3 ls
z80b
Am8001
IC HS 8167
z80 multibus
74LS240
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