STP2016
Abstract: SuperSPARC mbus 10 application STP2011 STP2016QFP mbus MCLK11 MOSC STP2012
Text: STP2016 July 1997 Clock-2 Generator System Clock Generator DATA SHEET DESCRIPTION The STP2016 Clock-2 Chip generates clock signals for components on the SBus and MBus. The MBus and SBus are used by SPARC processors, such as SuperSPARC™. The MBus is designed for multiprocessing MP , operating at
|
Original
|
STP2016
STP2016
64-bit
PQFP100
100-Pin
STP2016QFP
SuperSPARC
mbus 10 application
STP2011
STP2016QFP
mbus
MCLK11
MOSC
STP2012
|
PDF
|
RC1180-MBUS
Abstract: NTA8130 RC1180-MBUS2 marking code ABB SMD BLM18xx102xN1D AES-128 resistor 8k2 ohm RC1180-MBUS1 rf transceiver module RC1180
Text: Radiocrafts Embedded Wireless Solutions RC1180-MBUS Wireless M-Bus Multi-Mode RF Transceiver Module EN 13757-4:2005 Product Description The RC1180-MBUS RF Transceiver Module is a compact surface-mounted high performance module with embedded Wireless M-Bus protocol. The module has a UART interface for serial
|
Original
|
RC1180-MBUS
RC1180-MBUS
NO-0484
NTA8130
RC1180-MBUS2
marking code ABB SMD
BLM18xx102xN1D
AES-128
resistor 8k2 ohm
RC1180-MBUS1
rf transceiver module
RC1180
|
PDF
|
EN-13757
Abstract: EN-13757-4 EN13757-3 Wavecom fastrack supreme EN13757-1 DLMS Protocol wired m-bus RC1180-MBUS wavecom gprs application note mbus 10 application
Text: RC1180-MBUS Wireless M-Bus – Radio module The Wireless M-Bus module RC1180-MBUS from Radiocrafts, comes with different firmware feature sets, based on one standard hardware platform. The form factor, pin-out and interface are the same for all firmware versions. The MBUS2 feature set is compliant with NTA 8130 for
|
Original
|
RC1180-MBUS
RC1180-MBUS
NO-0484
EN-13757
EN-13757-4
EN13757-3
Wavecom fastrack supreme
EN13757-1
DLMS Protocol
wired m-bus
wavecom gprs application note
mbus 10 application
|
PDF
|
NOTE-AN067
Abstract: msp430 MBUS CC1101 MSP430 CC1101EM DN005 AN067 cc1101 RF interface with 8051 RF MODULE CC2500 CIRCUIT DIAGRAM correlation flow METER 8051 SWRA234
Text: Application Note AN067 Wireless MBUS Implementation with CC1101 and MSP430 By Patrick Seem Keywords • • • • • • 1 • • • • • Wireless MBUS KNX-RF Meter reading Data rate offset and drift Frequency offset and drift MSP430 Synchronization word
|
Original
|
AN067
CC1101
MSP430
CC1101
MSP430
SWRA234
NOTE-AN067
msp430 MBUS
CC1101 MSP430
CC1101EM
DN005
AN067
cc1101 RF interface with 8051
RF MODULE CC2500 CIRCUIT DIAGRAM
correlation flow METER 8051
SWRA234
|
PDF
|
free mbus master
Abstract: SuperSPARC VOLTAGE REGULATOR 78 IEEE754 SS20 STP1021A STP5011D STP5011DMBUS75 M-BUS mbus controllers
Text: STP5011D July 1997 SuperSPARC -II MBus Modules DATA SHEET 75/85 MHz SuperSPARC-II + 1 MB E-Cache DESCRIPTION The STP5011D is the MBus module incorporating the latest SuperSPARC-II microprocessor. This module provides a CPU sub-system with the high performance superscalar SuperSPARC-II microprocessor STP1021A
|
Original
|
STP5011D
STP5011D
STP1021A)
STP1091)
IEEE754
KByte021A.
STP5011DMBUS-75
free mbus master
SuperSPARC
VOLTAGE REGULATOR 78
SS20
STP1021A
STP5011DMBUS75
M-BUS
mbus controllers
|
PDF
|
lga60 FLASH
Abstract: No abstract text available
Text: Freescale Semiconductor Advance Information Document Number: MC12311 Rev. 1.0 11/2011 MC12311 Package Information Case nnnn-xx LGA-60 [8x8 mm] MC12311 Highly-integrated, cost-effective single-package solution for the sub-1 GHz, Wireless MBUS Standard
|
Original
|
MC12311
LGA-60
MC12311
HCS08
lga60 FLASH
|
PDF
|
EN-13757-4
Abstract: EN-13757 circuit diagram of 433 MHz rf transmitter and receiver of 6channel LGA60 LGA-60 EN13757-4 lga60 FLASH ADP62 MHz-928 MC12311RM
Text: Freescale Semiconductor Advance Information Document Number: MC12311 Rev. 1.0 11/2011 MC12311 Package Information Case nnnn-xx LGA-60 [8x8 mm] MC12311 Highly-integrated, cost-effective single-package solution for the sub-1 GHz, Wireless MBUS Standard
|
Original
|
MC12311
MC12311
LGA-60
EN-13757-4
EN-13757
circuit diagram of 433 MHz rf transmitter and receiver of 6channel
LGA60
LGA-60
EN13757-4
lga60 FLASH
ADP62
MHz-928
MC12311RM
|
PDF
|
EN-13757-4
Abstract: LGA60 ADP62 adp9 marking code 9S08QE32 LGA-60 flash LGA60 MC12311 EN137574 9S08
Text: Freescale Semiconductor Advance Information Document Number: MC12311 Rev. 0.0 09/2011 MC12311 Package Information Case nnnn-xx LGA-60 [8x8 mm] MC12311 Highly-integrated, cost-effective single-package solution for the sub-1 GHz, Wireless MBUS Standard
|
Original
|
MC12311
MC12311
LGA-60
EN-13757-4
LGA60
ADP62
adp9 marking code
9S08QE32
LGA-60
flash LGA60
EN137574
9S08
|
PDF
|
TMx390
Abstract: SuperSPARC STP1020 STP1021A MAD19 STP1091 ADDR02 Mbus master 250 slave circuit stp1090 imad-26
Text: STP1091.frm Page 97 Monday, August 25, 1997 3:08 PM STP1091 July 1997 Multi-Cache Controller DATA SHEET Integrated Cache Controller for SuperSPARC DESCRIPTION The STP1091 is a high-performance external cache controller for the STP1020 SuperSPARC and STP1021 (SuperSPARC-II) microprocessors. It is used when a large secondary cache or an interface to a non-MBus system is required.
|
Original
|
STP1091
STP1091
STP1020
STP1021
33x8k
TMx390
SuperSPARC
STP1020
STP1021A
MAD19
ADDR02
Mbus master 250 slave circuit
stp1090
imad-26
|
PDF
|
Untitled
Abstract: No abstract text available
Text: Wireless M-Bus Suite and Silabs specific documetation Quick Start Guide January 17, 2014 page 2 Document History 1.00 1.01 1.02 1.03 2013-10-11 2013-11-11 2013-11-14 2014-01-17 First release Setup chapter updated Note in chapter ’Firmware’ added Added chapter 4.1.4
|
Original
|
15-December-2011]
|
PDF
|
M-BUS
Abstract: mbus "7 Segment Display" 7-seg MBC5 mbus master AN10 MCF5307
Text: MCF5307 M-BUS INTERFACE MODULE 5307 M-BUS Motorola ColdFire 1- 1 M-BUS INTERFACE • TWO-WIRE, BIDIRECTIONAL SERIAL BUS FOR ON-BOARD COMMUNICATION • MULTI-MASTER OPERATION WITH ARBITRATION AND COLLISION DETECTION MCF5307 • CALLING ADDRESS RECOGNITION AND
|
Original
|
MCF5307
M-BUS
mbus
"7 Segment Display"
7-seg
MBC5
mbus master
AN10
MCF5307
|
PDF
|
SuperSPARC
Abstract: M-BUS
Text: Preliminary STP5011B SPARC Technology Business November 1994 60, 50 MHz SuperSPARC MBus Module DATA SHEET SuperSPARC + E-Cache MBus Module D e s c r i p t io n The STP501 IB is one of the members of the SuperSPARC based MBus module products. It is designed
|
OCR Scan
|
STP5011B
STP501
STP1020A)
STP1090A)
STP1020A
an100
STP5011BMB
US-50
SuperSPARC
M-BUS
|
PDF
|
supersparc
Abstract: No abstract text available
Text: Preliminary STP5010A SPARC Technology Business November 1994 5 0 MHz SuperSPARC MBus Module DATA SHEET SuperSPARC Only MBus Module D e s c r i p t io n The STP5010A is one of the members of the SuperSPARC based MBus module products. The STP5010A is designed with the latest high performance superscalar SuperSPARC STP1020A micro
|
OCR Scan
|
STP5010A
STP5010A
STP1020A)
Module-50
STP5010AMBUS-50
STP1020A
supersparc
|
PDF
|
mbus 10 application
Abstract: STP2012 TP2018
Text: S un M icroelectronics July 1997 Clock-2 Generator DATA SHEET System Clock Generator D e s c r ip t io n The STP2016 Clock-2 Chip generates clock signals for components on the SBus and MBus. The MBus and SBus are used by SPARC processors, such as SuperSPARC™. The MBus is designed for multiprocessing
|
OCR Scan
|
STP2016
64-bit
MCLK10
88S88g88
8S3885B
100-Pin
mbus 10 application
STP2012
TP2018
|
PDF
|
|
|
supersparc
Abstract: mbr d type 51 pins connector mbus controllers
Text: Preliminary ^ SPARC Technology Business STP5022B November 1994 Dual 50 MHz SuperSPARC MBus Module DATA SHEET Dual SuperSPARC + E-Cache Module D e s c r i p t io n The STP5022B is a dual SuperSPARC based MBus module. It is designed with the latest high perfor
|
OCR Scan
|
STP5022B
STP5022B
STP1020A)
STP1090A)
STP1020A
STP5022BMBUS-50
STP1020As,
STP1090As,
supersparc
mbr d type 51 pins connector
mbus controllers
|
PDF
|
STP2012
Abstract: SuperSPARC STP2016QFP
Text: STP2016 S un M ic r o e l e c t r o n ic s J u ly 1997 Clock-2 Generator DATA SHEET System Clock Generator D e s c r ip t io n The STP2016 Clock-2 Chip generates clock signals for components on the SBus and MBus. The MBus and SBus are used by SPARC processors, such as SuperSPARC™. The MBus is designed for multiprocessing MP , operating at
|
OCR Scan
|
STP2016
STP2016
64-bit
100-Pin
STP2016Q
STP2012
SuperSPARC
STP2016QFP
|
PDF
|
mrd 14b
Abstract: ba1643
Text: • 5 3 0 4 0 0 4 O O l E S L b 07^ L L C L64862 Mbus to Sbus Interface MSI Technical Manual Publication ID: M 14023 Publication Date: October 1, 1992 Company: L S I LOGIC CORP This title page is provided as a service by Inform ation Handling Services and displays
|
OCR Scan
|
L64862
0012Sfc
SparKIT-40/SS
mrd 14b
ba1643
|
PDF
|
Untitled
Abstract: No abstract text available
Text: Order this data sheet by MC16LX952/D MOTOROLA SEMICONDUCTOR TECHNICAL DATA M C 16LX952 16-Bit Bi-Directional Register With Clock Enable A LE V S 3-S tate, Non-Inverting Features 16-BIT BI-DIRECTIONAL REGISTER WITH CLOCK ENABLE • A Member of Motorola’s A LE xlS 'MBus Interface Solutions Family
|
OCR Scan
|
MC16LX952/D
16-Bit
64-Lead,
64mA/-32mA
500mA
3PHX32081-1
|
PDF
|
m-bus c#
Abstract: No abstract text available
Text: S T P 5011D S un M ic r o e le c t r o n ic s J u ly 1997 SuperSPARC -ll MBus Modules DATA SHEET 75/85 MHz SuperSPARC-II + 1 MB E-Cache D e s c r ip t io n The STP5011D is the M Bus m odule incorporating the latest SuperSFARC-II microprocessor. This m odule pro
|
OCR Scan
|
5011D
STP5011D
STP1021A)
STP1091)
IEEE754
STP501
STP5011D
m-bus c#
|
PDF
|
Untitled
Abstract: No abstract text available
Text: STP5011D S un M ic r o e l e c t r o n ic s J u ly 1997 SuperSPARC”-ll MBus Modules DATA SHEET 75/85 MHz SuperSPARC-II + 1 MB E-Cache D e s c r ip t io n The STP5011D is the M Bus m odule incorporating the latest SuperSPARC-II microprocessor. This m odule pro
|
OCR Scan
|
STP5011D
STP5011D
STP1021A)
STP1091)
IEEE754
5011DMBUS-75
|
PDF
|
6253A
Abstract: supersparc
Text: S un M icroelectronics July 1997 SuperSPARCT"-ll MBus Modules DATA SHEET 75/85 MHz SuperSPARC-II + 1 MB E-Cache D e s c r ip t io n The STP5011D is the M Bus m odule incorporating the latest SuperSPARC-II microprocessor. This m odule pro vides a CPU sub-system with the high perform ance superscalar SuperSPARC-II microprocessor STP1021 A
|
OCR Scan
|
STP5011D
STP1021
STP1091)
IEEE754
STP1021A
STP5011D
6253A
supersparc
|
PDF
|
SuperSPARC
Abstract: Mbus master 250 slave circuit tmx390 STP1091-60
Text: S un M icroelectronics July 1997 Multi-Cache Controller DATA SHEET Integrated Cache Controller for SuperSPARC D e s c r ip t io n The STP1091 is a high-performance external cache controller for the STP1020 SuperSPARC and STP1021 (SuperSPARC-II) microprocessors. It is used when a large secondary cache or an interface to a non-MBus sys
|
OCR Scan
|
STP1091
STP1020
STP1021
33x8k
STP1091PGA-75
STP1091PGA-90
STP1020HS
STP1091
SuperSPARC
Mbus master 250 slave circuit
tmx390
STP1091-60
|
PDF
|
Untitled
Abstract: No abstract text available
Text: STP2016 S un M ic r o e l e c t r o n ic s J u ly 1 9 9 7 Clock-2 Generator System Clock Generator DATA SHEET D e s c r ip t io n The STP2016 Clock-2 Chip generates clock signals for com ponents on the SBus and MBus. The M Bus and SBus are used by SPARC processors, such as SuperSPARC™. The M Bus is designed for multiprocessing
|
OCR Scan
|
STP2016
STP2016
64-bit
100-Pin
TP2016Q
|
PDF
|
ML4008
Abstract: L64811 l64844 L64852 SparKIT-20 pc motherboard schematics L64801 L64854 L64825
Text: 5304ÔQ4 001DE53 < ^ 3 « L L C After the SPARCstation from Sun Microsystems became an international workstation standard, vendors began to show increasing interest in the SPARC-compatible market in the United States, along the Pacific rim, and in Europe. To facilitate the design of
|
OCR Scan
|
001DE53
SPECint92
SPECfp92
SS101
SparKIT-40/Mbus
L64831
SparKIT-40/SS2
L64811
IU/L64814
SparKIT-20+
ML4008
l64844
L64852
SparKIT-20
pc motherboard schematics
L64801
L64854
L64825
|
PDF
|
