KEIL
Abstract: No abstract text available
Text: PSoC Creator Component Datasheet I2C Master/Multi-Master/Slave 3.30 Features • Industry-standard NXP® I2C bus interface • Supports slave, master, multi-master and multi-master-slave operation Requires only two pins SDA and SCL to interface to I2C bus
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Abstract: No abstract text available
Text: PSoC Creator Component Datasheet I2C Master/Multi-Master/Slave 3.10 Features • Industry-standard NXP® I2C bus interface • Supports slave, master, multi-master and multi-master-slave operation Requires only two pins SDA and SCL to interface to I2C bus
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Abstract: No abstract text available
Text: PSoC Creator Component Datasheet I2C Master/Multi-Master/Slave 3.0 Features • Industry-standard NXP® I2C bus interface • Supports Slave, Master, Multi-Master and Multi-Master-Slave operation Only two pins SDA and SCL required to interface to I2C bus
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Abstract: No abstract text available
Text: PSoC Creator Component Datasheet I2C Master/Multi-Master/Slave 3.20 Features • Industry-standard NXP® I2C bus interface • Supports slave, master, multi-master and multi-master-slave operation Requires only two pins SDA and SCL to interface to I2C bus
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Abstract: No abstract text available
Text: PSoC Creator Component Datasheet I2C Master/Multi-Master/Slave 3.1 Features • Industry-standard NXP® I2C bus interface • Supports slave, master, multi-master and multi-master-slave operation Requires only two pins SDA and SCL to interface to I2C bus
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RNW RESISTOR
Abstract: arbitrage verilog code for I2C MASTER
Text: PSoC Creator Component Data Sheet I2C Master/Multi-Master/Slave 2.10 Features • Industry standard Philips® I2C bus interface • Supports Slave, Master, Multi-Master and Multi-Master-Slave operation • Only two pins SDA and SCL required to interface to I2C bus
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Abstract: No abstract text available
Text: PSoC Creator Component Datasheet I2C Master/Multi-Master/Slave 2.20 Features • Industry standard Philips® I2C bus interface • Supports Slave, Master, Multi-Master and Multi-Master-Slave operation Only two pins SDA and SCL required to interface to I 2C bus
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pci core
Abstract: Soft Core RTL FIFO synchronous fifo design in verilog
Text: PCI Peripheral Core PCI ADOUT Register Core Block Diagram PCI Parity Multiplexer Register Master Write FIFO PCI Bus Register Master Read FIFO Master State Machine/ DMA Register Master Request FIFO Output Mux Application Interface PCI I/O Cells ▼ Configuration
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32-bit
64-bit
ASIC-FS-20827-10/99
pci core
Soft Core RTL FIFO
synchronous fifo design in verilog
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Application Notes
Abstract: AVR32109 Master sequence device I2C TWI AVR32107 AVR32
Text: AVR32107: Using TWI as a Master on the AVR32 Features - Compatible with Philips' I2C protocol Master transmitter mode Master receiver mode 7-bit slave address – up to 127 devices on the same bus Normal 100kbps and Fast (400kbps) operation Interrupt driven communication
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AVR32107:
AVR32
100kbps)
400kbps)
32-bit
2011A-AVR-04/06
Application Notes
AVR32109
Master sequence device
I2C TWI
AVR32107
AVR32
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C500-ZL3AT1-E
Abstract: SRM1-C01-V1 CQM1-PRO01-E C200H-PRO27-E SRM1-C02-V1 SRM1-C01 ladder diagram
Text: Master Control Unit SRM1-C01-V1/C02-V1 Subminiature, Stand-alone Model with CompoBus/S Master and SYSMAC Controller Functions Maximum number of Remote I/O points per Master: 256 Maximum number of Slaves per Master: 32 Communications cycle time: 0.5 or 0.8 ms
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SRM1-C01-V1/C02-V1
RS-232C
SRM1-C02-V1)
RS-232C
SRM1-C01-V1
SRM1-C02-V1
inputs/128
inputs/64
C500-ZL3AT1-E
SRM1-C01-V1
CQM1-PRO01-E
C200H-PRO27-E
SRM1-C02-V1
SRM1-C01
ladder diagram
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eeprom 24c04
Abstract: 014b signetics 24C04 24CXX 24LC01 24LC04 AN554 PIC16C64 PIC16C71 PIC16C74
Text: Software Implementation of I2C Bus Master AN554 Software Implementation of I2C Bus Master In most systems the microcontroller is the master and the external peripheral devices are slaves. In these cases this application note can be used to attach I2C slaves to the PIC16CXX the master microcontroller.
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AN554
PIC16CXX
eeprom 24c04
014b signetics
24C04
24CXX
24LC01
24LC04
AN554
PIC16C64
PIC16C71
PIC16C74
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RS-232 to i2c converter
Abstract: i2c to RS-232 converter SC18IM700 FPGA with i2c eeprom RS-232 chip to i2c converter RS-232 to spi converter SC18IM700IPW SC18IS600 SC18IS600IPW SC18IS601
Text: NXP I2C master bridges SC18IS600/601 and SC18IM700 Low-power bridges for SPI slave or UART to I2C master or GPIO These compact protocol converters create seamless, low-power, low-voltage interface connections, so they make it quick and easy to add I2C master and GPIO capability to any
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SC18IS600/601
SC18IM700
RS-232 to i2c converter
i2c to RS-232 converter
SC18IM700
FPGA with i2c eeprom
RS-232 chip to i2c converter
RS-232 to spi converter
SC18IM700IPW
SC18IS600
SC18IS600IPW
SC18IS601
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VIC068A
Abstract: 68020 motorola
Text: 1.5 VIC068A VMEbus Master Operations The transfer of data is initiated by a VMEbus master module. The master module controls the type of transfer read, write, interrupt acknowledge, etc. and provides the address and address modifiers for the transfer. The timing of the start of the transfer is also controlled by the master.
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VIC068A
68020 motorola
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9541A
Abstract: I2C-bus specification 3 HVQFN16 JESD22-A114 JESD22-A115 JESD78 TSSOP16 PCA9541AD-01 PCA9541A
Text: PCA9541A 2-to-1 I2C-bus master selector with interrupt logic and reset Rev. 03 — 16 July 2009 Product data sheet 1. General description The PCA9541A is a 2-to-1 I2C-bus master selector designed for high reliability dual master I2C-bus applications where system operation is required, even when one master
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PCA9541A
PCA9541A
9541A
I2C-bus specification 3
HVQFN16
JESD22-A114
JESD22-A115
JESD78
TSSOP16
PCA9541AD-01
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Untitled
Abstract: No abstract text available
Text: SCANSTA101 SCANSTA101 Low Voltage IEEE 1149.1 System Test Access STA Master Literature Number: SNLS057I SCANSTA101 Low Voltage IEEE 1149.1 System Test Access (STA) Master General Description Features The SCANSTA101 is designed to function as a test master
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SCANSTA101
SCANSTA101
SNLS057I
SCANPSC100.
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JESD22-A114
Abstract: JESD22-A115 JESD78 PCA9541 TSSOP16 PCA9541A
Text: PCA9541A 2-to-1 I2C-bus master selector with interrupt logic and reset Rev. 02 — 4 June 2009 Product data sheet 1. General description The PCA9541A is a 2-to-1 I2C-bus master selector designed for high reliability dual master I2C-bus applications where system operation is required, even when one master
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PCA9541A
PCA9541A
JESD22-A114
JESD22-A115
JESD78
PCA9541
TSSOP16
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Untitled
Abstract: No abstract text available
Text: PCI 9060SD MAY 1996 VERSION 0.6 PCI Bus Master Interface Chip for Master and Slave Adapters General Description _ Featu res_ • • PCI Specification 2.1 compliant PCI Bus Master Interface supporting master and slave adapters
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9060SD
PCI9060SD
9060SD.
hflSS14^
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82355
Abstract: 29025
Text: IF^IlDMDRyw intei 82355 BUS MASTER INTERFACE CONTROLLER BMIC • Designed for use in 32-Bit EISA Bus Master Expansion Board Designs — Integrates Three Interfaces (EISA, Local CPU, and Transfer Buffer) Supports Automatic Handling of Complete EISA Bus Master Protocol
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32-Bit
132-Pin
24-Byte
82355
29025
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Untitled
Abstract: No abstract text available
Text: PCI 9060SD T E C H N □ L □ EY November 1995 PRELIMINARY VERSION 0.5 PCI Bus Master Interface Chip for Master and Slave Adapters General Description_ Featu res_ • • PCI Specification 2.1 compliant PCI Bus Master Interface supporting master and
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9060SD
PCI9060SD
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iso 4903
Abstract: 9060SD I960CX PCI9060SD
Text: PCI 9060SD T E C H N D L Q B Y MAY 1996 VERSION 0.6 PCI Bus Master Interface Chip for Master and Slave Adapters Feat u res_ General Description _ • • PCI Specification 2.1 compliant PCI Bus Master Interface supporting master and
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g-w50r--coo'
PCI9060SD
9060SD.
iso 4903
9060SD
I960CX
PCI9060SD
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6SS4
Abstract: LA 7681 LA01 9060SD I960CX PCI9060SD Pgti
Text: T E C H N D L U PCI 9060SD E Y A November 1995 PRELIMINARY VERSION 0.5 PCI Bus Master Interface Chip for Master and Slave Adapters General Description_ Featu res_ • • PCI Specification 2.1 compliant PCI Bus Master Interface supporting master and
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9060SD
80960SX
PCI9060SD
6SS4
LA 7681
LA01
9060SD
I960CX
PCI9060SD
Pgti
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82355
Abstract: No abstract text available
Text: 82355 The 82355 Bus Master Interface Controller BMIC is a highly integrated Bus Master designed for use in 32-Bit EISA Bus Master expansion board designs and supports all of the enhancements defined in the EISA specifications required for EISA bus master ap
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32-Bit
16and
82355
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Untitled
Abstract: No abstract text available
Text: VSB 1400 Æ X - VSB Master Module Interface Device Tu May 1989_ Distinctive Features_ Applications_ • Bus interface circuitry for multi-master VSB systems • VSB master chip contains - Single level arbiter
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24-Lead
28-Pin
DGD02S2
24-Pin
10TYP
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Untitled
Abstract: No abstract text available
Text: Æ X - VSB 1400 T• VSB Master Module Interface Device May 1989_ Distinctive Features_ Applications_ • Bus interface circuitry for multi-master VSB systems • VSB master chip contains - Single level arbiter
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