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    MACRO Search Results

    MACRO Result Highlights (2)

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    ADL5335ACPZN-R7 Analog Devices Macro Tx DGA Visit Analog Devices Buy
    ADL5335ACPZN Analog Devices Macro Tx DGA Visit Analog Devices Buy
    SF Impression Pixel

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    SRA Soldering Products AO9378+MACRO

    AOYUE INT 9378 PRO WITH MACRO TW
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    DigiKey AO9378+MACRO Box 3 1
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    Fluke Corporation FLK MACRO LENS

    INFRARED MACRO LENS
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    Fluke Corporation FLK-XLENS/MACRO1

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    SRA Soldering Products AO9378-220-MACRO

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    OMRON Corporation PLATE, BOTTOM, MACRO & I/O INT

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    MACRO Datasheets (500)

    Part ECAD Model Manufacturer Description Curated Type PDF
    23C1010 Macronix International 1M-BIT MASK ROM (8 BIT OUTPUT) Original PDF
    23C2000 Macronix International 2M-BIT MASK ROM (8 BIT OUTPUT) Original PDF
    23C4000 Macronix International 4M-BIT MASK ROM (8 BIT OUTPUT) Original PDF
    23C4096 Macronix International 524,288 x 8-bit CMOS ROM Scan PDF
    23C4096A Macronix International 524,288 x 8-bit CMOS ROM Scan PDF
    23C4096B Macronix International 524,288 x 8-bit CMOS ROM Scan PDF
    23C4100-10 Macronix International 4M-BIT [512K x 8/256K x 16] MASK ROM Original PDF
    23C4100-12 Macronix International 4M-BIT [512K x 8/256K x 16] MASK ROM Original PDF
    23C4100-15 Macronix International 4M-BIT [512K x 8/256K x 16] MASK ROM Original PDF
    23C6410 Macronix International 64M-BIT Mask ROM (8/16 Bit Output) For SOP and TSOP Packages Original PDF
    23L12810A-10 Macronix International 128M-BIT PAGE MODE MASK ROM (SOP) Original PDF
    23L12811-10 Macronix International 128M-BIT (8M x 16) MASK ROM WITH PAGE MODE(SOP ONLY) Original PDF
    23L12824-12 Macronix International 128M-BIT MASK ROM Original PDF
    23L25611-10 Macronix International 256M-BIT (16M x 16 / 32M x 8) MASK ROM WITH PAGE MODE (SSOP ONLY) Original PDF
    23L3212-90 Macronix International 32M-BIT MASK ROM Original PDF
    23L51220-90 Macronix International 512M-BIT (16M x 32) MASK ROM WITH PAGE MODE (SSOP ONLY) (for socket solution only) Original PDF
    27C1024 Macronix International 1M-BIT [128K x 8/64K x 16] CMOS EPROM Original PDF
    27C1610-10 Macronix International 16M-BIT [2M x 8/1M x 16] CMOS OTP ROM Original PDF
    27C1610-12 Macronix International 16M-BIT [2M x 8/1M x 16] CMOS OTP ROM Original PDF
    27C2000 Macronix International 2M-BIT [256K x 8] CMOS EPROM Original PDF
    ...

    MACRO Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    Untitled

    Abstract: No abstract text available
    Text: MAX3785 Output Model 6.25Gbps 1.8V Board Equalizer SPICE I/O Macromodels aid in understanding signal integrity issues in electronic systems. Most of Maxim’s High Frequency/Fiber Communication ICs utilize input and output I/O circuits with Current Mode Logic (CML), Positive Emitter Coupled Logic


    Original     		PDF MAX3785 25Gbps worst-c28 REPORTERL1N29 REPORTERL1N30 920E-018 DE0900A DE0396 REPORTERL1N27 REPORTERL1N28

    NET0260

    Abstract: 3845 n equivalent VALUE IC net219 LTspice eldo TSH300
    Text: Development of the Analog Macromodel for TSH300, ultra low-noise high-speed operational amplifier Angelo Marotta angelo.marotta@st.com STMicroelectronics May 2011 Abstract An unified analog macromodel, for Spice-like simulators, was implemented for TSH300 operational amplifier matching the real DC, Transient and AC behavior


    Original     		PDF TSH300, TSH300 NET0260 3845 n equivalent VALUE IC net219 LTspice eldo

    NMTC-S40200XFYHSAY

    Abstract: Character characters KS0066 KS0066U
    Text: Microtips Technology Inc. 台北縣汐止鎮康寧街169巷31號12樓 Microtips Technology 12F, No 31, Lane 169, Kang Ning St. Hsi-Chih, Taipei Hsien, Taiwan, R.O.C. WEB : http://www.microtips.com.tw E-mail : Macros@microtips.com.tw TEL: 886-2-2695-3133 FAX :886-2-2695-8625


    Original     		PDF NMTC-S40200XFYHSAY NMTC-S40200XFYHSAY Character characters KS0066 KS0066U

    cypress flash 370

    Abstract: logic block diagram of cypress flash 370 device 22v10 CY7C375 FLASH370 o112i cypress flash 370 CPLD cypress flash 370 device technology
    Text: fax id: 6130 For new designs see CY7C375i CY7C375 UltraLogic 128-Macrocell Flash CPLD Features Functional Description • 28 macrocells in eight logic blocks • 28 I/O pins • 6 dedicated inputs including 4 clock pins • Bus Hold capabilities on all I/Os and dedicated inputs


    Original     		PDF CY7C375i CY7C375 128-Macrocell CY7C375 LASH370TM FLASH370 22V10 I/O112-I/O127 cypress flash 370 logic block diagram of cypress flash 370 device o112i cypress flash 370 CPLD cypress flash 370 device technology

    ATV2500BQ

    Abstract: ATV2500B ATV2500BL ATV2500BQL
    Text: Features • High Performance, High Density Programmable Logic Device – Typical 7 ns Pin-to-Pin Delay – Fully Connected Logic Array With 416 Product Terms • Flexible Output Macrocell – 48 Flip-Flops - Two per Macrocell – 72 Sum Terms – All Flip-Flops, I/O Pins Feed In Independently


    Original     		PDF ATV2500B ATV2500BQ ATV2500BL ATV2500BQL I/O17 I/O16 I/O15 I/O14 I/O13 I/O12 ATV2500BQ ATV2500B ATV2500BL ATV2500BQL

    XC9572

    Abstract: XC9572-10PC44C xc9572-15PQ100 15PC44I xc9572 data sheet XC9572-7PC44C PC44 PC84 xc9572-10pq100c XC9572-15PC84C
    Text: XC9572 In-System Programmable CPLD R DS065 v4.2 April 15, 2005 5 Product Specification Features Description • • 7.5 ns pin-to-pin logic delays on all pins fCNT to 125 MHz • • • 72 macrocells with 1,600 usable gates Up to 72 user I/O pins 5V in-system programmable


    Original     		PDF XC9572 DS065 36V18 XC9572-10PC44C xc9572-15PQ100 15PC44I xc9572 data sheet XC9572-7PC44C PC44 PC84 xc9572-10pq100c XC9572-15PC84C

    7C344-25

    Abstract: C344 74HC CY7C344 Signal Path Designer C3445
    Text: CY7C344 32-Macrocell MAX EPLD Features tional I/O pins communicate to one logic array block. In the CY7C344 LAB there are 32 macrocells and 64 expander product terms. When an I/O macrocell is used as an input, two expanders are used to create an input path. Even if all of the


    Original     		PDF CY7C344 32-Macrocell CY7C344 28-pin, 300-mil 28-pin 7C344-25 C344 74HC Signal Path Designer C3445

    XCR3128XL-10VQ100I

    Abstract: XCR3128XL-10TQ144I XCR3128XL-7CS144I XCR3128XL XCR3128XL-10CS144I XCR3128XL-10VQ100C CS144 marking E13 diode L12M1 k3296
    Text: R XCR3128XL 128 Macrocell CPLD DS016 v2.1 August 21, 2003 14 Preliminary Product Specification Features Description • Low power 3.3V 128 macrocell CPLD • 6.0 ns pin-to-pin logic delays • System frequencies up to 175 MHz • 128 macrocells with 3,000 usable gates


    Original     		PDF XCR3128XL DS016 144-pin 144-ball 100-pin XCR3128XL-10VQ100I XCR3128XL-10TQ144I XCR3128XL-7CS144I XCR3128XL-10CS144I XCR3128XL-10VQ100C CS144 marking E13 diode L12M1 k3296

    PT80

    Abstract: No abstract text available
    Text: ispLSI 81080V Features Functional Block Diagram • SuperBIG HIGH DENSITY IN-SYSTEM PROGRAMMABLE LOGIC — 3.3V Power Supply — 60,000 PLD Gates/1080 Macrocells — 192-360 I/O Pins Supporting 3.3V/2.5V I/O — 1440 Registers — High-Speed Global and Big Fast Megablock BFM


    Original     		PDF 1080V Gates/1080 20-Macrocell 492-Ball 0212/81080V 1080V-125LB272 272-Ball 1080V-125LB492 1080V-90LB272 PT80

    Programmable Divider

    Abstract: 20MHZ 400M AL2007LA STD90 embedded PLL divider
    Text: 0.35µ µm 20MHZ-170MHZ FSPLL AL2007LA GENERAL DESCRIPTION The AL2007LA is a Phase-Locked Loop PLL frequency synthesizer constructed in CMOS on single monolithic structure. The PLL macrofunctions provide frequency multiplication capabilities. The output clock frequency Fout is related to the reference input clock frequency Fin by the following equation:


    Original     		PDF 20MHZ-170MHZ AL2007LA AL2007LA Programmable Divider 20MHZ 400M STD90 embedded PLL divider

    MoSys

    Abstract: CL018G tsmc 0.18um MoSys sram embedded BWEB M1T1HT18PZ32E C-l018 32K32 MoSys 1T sram
    Text: High Speed Pipelined 1-Mbit 32Kx32 Standard 1T-SRAM Embedded Memory Macro M1T1HT18PZ32E • High Performance 1T-SRAM Standard Macro • 200 MHz operation • 1-Clock cycle time • Pipelined read access timing • Late-late write mode timing • 32-Bit wide data buses


    Original     		PDF 32Kx32) M1T1HT18PZ32E 32-Bit CL018G 2300um 32Kx32 1650um M1T1HT18PZ32E MoSys tsmc 0.18um MoSys sram embedded BWEB C-l018 32K32 MoSys 1T sram

    TPUMASMREF

    Abstract: LF 324 M68300 M68HC16 SR15 X123 AU113 DSA00207913
    Text: Time Processor Unit Macro Assembler TPUMASM Reference Manual This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice. Motorola reserves the right to make changes without further notice to any products herein to improve reliability,


    Original     		PDF

    XCR5128

    Abstract: MC16 XCR3128 Xilinx XCR5128 P-QFP40
    Text: APPLICATION NOTE This product has been discontinued. Please see www.xilinx.com/partinfo/notify/pdn0007.htm for details. R DS041 v1.4 January 19, 2001 XCR5128: 128 Macrocell CPLD 14* Product Specification Features Description • The XCR5128 CPLD (Complex Programmable Logic


    Original     		PDF com/partinfo/notify/pdn0007 DS041 XCR5128: XCR5128 100-pin VQ100: TQ128: 128-pin MC16 XCR3128 Xilinx XCR5128 P-QFP40

    Physical Layer Controllers

    Abstract: W812 W812-F
    Text: W812 IEEE 1304-1195 Page -1 Monday, January 26, 1998 5:42 PM Technical Brief O K I A S I C P R O D U C T S W812 IEEE 1394 Controller 0.35 µm Technology Mega Macrofunction November 1997 W812 IEEE 1304-1195 Page 0 Monday, January 26, 1998 5:42 PM • ■ –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––


    Original     		PDF 1-800-OKI-6994 Physical Layer Controllers W812 W812-F

    MACH130-20

    Abstract: MACH130 MACH230 PAL22V10 PAL26V16
    Text: FINAL COM’L: -15/20 IND: -18/24 MACH130-15/20 Lattice Semiconductor High-Density EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS 84 Pins 64 Outputs 64 Macrocells 64 Flip-flops; 4 clock choices 15 ns tPD Commercial 18 ns tPD Industrial 4 “PAL26V16” Blocks


    Original     		PDF MACH130-15/20 PAL26V16" MACH131, MACH230, MACH231, MACH435 MACH130 PAL22V10 14131H-26 MACH130-20 MACH230 PAL26V16

    Untitled

    Abstract: No abstract text available
    Text: CY7C371i UltraLogic 32-Macrocell Flash CPLD Features signed to bring the ease of use and high performance of the 22V10, as well as PCI Local Bus Specification support, to high-density CPLDs. • • • • 32 macrocells in two logic blocks 32 I/O pins


    Original     		PDF CY7C371i 32-Macrocell 22V10, FLASH370i

    resistor temprature detector datasheet

    Abstract: Temprature controlled oscillator BW2010P ID16
    Text: 25MHz ~ 250MHz FSPLL BW2010P FEB. 2000. Ver1.2.21 General Description Features The BW2010P is a Phase-Locked Loop PLL frequency synthesizer constructed in CMOS process technology. The PLL macrofunctions provide frequency multiplication capabilities.The output clock frequency, Fout, is related to the


    Original     		PDF 25MHz 250MHz BW2010P BW2010P resistor temprature detector datasheet Temprature controlled oscillator ID16

    XC95144XL-10TQ144I

    Abstract: XC95144XL-10TQG100C XAPP114 XAPP427 XC9500XL XC95144 XC95144XL XC95144XL-5-CS144 XC95144XL-5TQ100 xc95144xl tq144
    Text: XC95144XL High Performance CPLD R DS056 v1.8 July 15, 2005 5 Product Specification Features Power Estimation • • • • Power dissipation in CPLDs can vary substantially depending on the system frequency, design application and output loading. To help reduce power dissipation, each macrocell


    Original     		PDF XC95144XL DS056 XC9500XL CS144 220oC. XC95144XL-10TQ144I XC95144XL-10TQG100C XAPP114 XAPP427 XC95144 XC95144XL-5-CS144 XC95144XL-5TQ100 xc95144xl tq144

    PAL26V12

    Abstract: MACH120 MACH220 PAL22V10
    Text: FINAL COM’L: -10/12/15/20 IND: -14/18/24 MACH220-10/12/15/20 Lattice Semiconductor High-Density EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS 68 Pins 48 Outputs 96 Macrocells 96 Flip-flops; 4 clock choices 10 ns tPD 8 “PAL26V12” blocks with buried macrocells


    Original     		PDF MACH220-10/12/15/20 PAL26V12" MACH120 MACH221 MACH220 PAL22V10 14130I-26 14130I-27 PAL26V12

    20RA10

    Abstract: 20RA10-15 PLDC20RA10 PLDC20RA10-15JC RA1021
    Text: fax id: 6015 1P LDC20 RA10 PLDC20RA10 Reprogrammable Asynchronous CMOS Logic Device Features • • • • • • • • • — ICC max = 85 mA Military • High reliability — Proven EPROM technology Advanced-user programmable macrocell CMOS EPROM technology for reprogrammability


    Original     		PDF LDC20 PLDC20RA10 20RA10 20RA10-15 PLDC20RA10 PLDC20RA10-15JC RA1021

    lf XTAL 20MHz

    Abstract: XTAL 20MHz 20MHZ PLL2013X STD110
    Text: 0.25µ µm 20MHz~170MHz FSPLL PLL2013X GENERAL DESCRIPTION The PLL2013X is a Phase-Locked Loop PLL frequency synthesizer constructed in CMOS on single monolithic structure. The PLL macro-functions provide frequency multiplication capabilities. The output clock frequency Fout is related to the input clock frequency Fin(XTALIN) by the following equation:


    Original     		PDF 20MHz 170MHz PLL2013X PLL2013X VDD25A1 VSS25A1 lf XTAL 20MHz XTAL 20MHz STD110

    HCMOS9

    Abstract: SATA310
    Text: ST SATA310 Ideal for serial ATA and easily adapted to support SAS interfaces Offering high-performance, low-power, low-cost, and a modular design, the SATA310 is available as a fully characterized macro-cell for highly integrated SOC solutions, using STMicroelectronics’ advanced HCMOS9


    Original     		PDF SATA310 SATA310 75MHz 150MHz 20-bit 8b/10bST HCMOS9

    62A17

    Abstract: HCA62A17 62A50 18PDIP 68-LCC
    Text: í Order this data sheet by HCA62A00/D M MOTOROLA HCA62A00 Series SEM ICO NDUCTO RS P.O B O X 20912 • PHOENIX, A R IZ O N A 85036 HCA62A00 SERIES CMOS MACROCELL ARRAYS The HCA62A00 series m acrocell arrays are im plem ented in sil­ icon gate, 2-m icron draw n gate length, dual-layer metal intercon­


    OCR Scan     		PDF HCA62A00/D HCA62A00 62A17 HCA62A17 62A50 18PDIP 68-LCC

    parallel to serial conversion

    Abstract: diode 1432
    Text: Temic COMLIB MATRA MHS ATM Physical Layer ASIC Macro Library for 1.432 Description The ASIC Macro Library is consisting of specific macros which are supporting the ATM 1.432 Physical M edium Sublayer up to 622 MBit/s serial communication. This macro family, which is targeted


    OCR Scan     		PDF