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    Silicon Laboratories Inc BGM13S32F512GA-V3

    RF TXRX MODULE BT CHIP SMD
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    DigiKey BGM13S32F512GA-V3 Tray 4,787 1
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    Mouser Electronics BGM13S32F512GA-V3 6,013
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    C&K PCM13SMTR

    SWITCH SLIDE SP3T 300MA 6V
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    Mouser Electronics PCM13SMTR 3,597
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    TTI PCM13SMTR Reel 3,000
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    TME PCM13SMTR 2,450 2
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    JRH Electronics 660-049XM13S3-13

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    DigiKey 660-049XM13S3-13 Bulk 200 1
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    JRH Electronics 661-002M13S5-02

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    DigiKey 661-002M13S5-02 Bulk 92 1
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    JRH Electronics 660-024M13S4-06

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    DigiKey 660-024M13S4-06 Bulk 52 1
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    M13S Datasheets (24)

    Part ECAD Model Manufacturer Description Curated Type PDF
    M13S128168A Elite Semiconductor Memory Technology 2M x 16 Bit x 4 Banks Double Data Rate SDRAM Original PDF
    M13S128168A Unknown 2M x 16 Bit x 4 Banks Double Data Rate SDRAM Original PDF
    M13S128168A-5T Elite Semiconductor Memory Technology 2M x 16 Bit x 4 Banks Double Data Rate SDRAM Original PDF
    M13S128168A-5T Elite Semiconductor Memory Technology 2M x 16 Bit x 4 Banks Double Data Rate SDRAM Original PDF
    M13S128168A-5TG Unknown 2M x 16 Bit x 4 Banks Double Data Rate SDRAM Original PDF
    M13S128168A-6T Elite Semiconductor Memory Technology 2M x 16 Bit x 4 Banks Double Data Rate SDRAM Original PDF
    M13S128168A-6T Elite Semiconductor Memory Technology 2M x 16 Bit x 4 Banks Double Data Rate SDRAM Original PDF
    M13S128168A-6TG Unknown 2M x 16 Bit x 4 Banks Double Data Rate SDRAM Original PDF
    M13S128168A-7.5AB Elite Memory Technology 2M x 16 Bit x 4 Banks Double Data Rate SDRAM Original PDF
    M13S128168A-7.5AB Elite Semiconductor Memory Technology 2M x 16-Bit x 4 Banks Double Data Rate SDRAM Original PDF
    M13S128324A Elite Semiconductor Memory Technology 1M x 32 Bit x 4 Banks Double Data Rate SDRAM Original PDF
    M13S128324A Unknown Modify typing error of Pin Arrangement Original PDF
    M13S128324A-5BG Unknown Modify typing error of Pin Arrangement Original PDF
    M13S128324A-6BG Unknown Modify typing error of Pin Arrangement Original PDF
    M13S2561616A Elite Semiconductor Memory Technology 4M x 16 Bit x 4 Banks Double Data Rate SDRAM Original PDF
    M13S2561616A-4TG Elite Semiconductor Memory Technology 4M x 16 Bit x 4 Banks Double Data Rate SDRAM Original PDF
    M13S2561616A-5TG Elite Semiconductor Memory Technology 4M x 16 Bit x 4 Banks Double Data Rate SDRAM Original PDF
    M13S2561616A-6TG Elite Semiconductor Memory Technology 4M x 16 Bit x 4 Banks Double Data Rate SDRAM Original PDF
    M13S256328A Elite Semiconductor Memory Technology 2M x 32 Bit x 4 Banks Double Data Rate SDRAM Original PDF
    M13S32321A Elite Semiconductor Memory Technology 256K x 32 Bit x 4 Banks Double Data Rate SDRAM Original PDF

    M13S Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    Untitled

    Abstract: No abstract text available
    Text: ESMT M13S128168A Operation temperature condition -40°C~85°C Revision History Revision 1.0 03 Jan. 2007 - Original Revision 1.1 (19 Mar. 2008) - Add BGA package - Modify the waveform of Power up & Initialization Sequence - Modify the θ value of TSOPII package dimension


    Original     		PDF M13S128168A

    Untitled

    Abstract: No abstract text available
    Text: ESMT M13S2561616A Revision History Revision 0.1 28 Apr. 2006 - Original Revision 1.0 (07 Jun. 2006) - Delete Preliminary at ever page - Revise typing error of page1 Revision 1.1 (09 May. 2007) - Modify PD, DC specifications and MRS Revision 1.2 (12 Jun. 2007)


    Original     		PDF 66-Lead M13S2561616A M13S25616

    Untitled

    Abstract: No abstract text available
    Text: ESMT M13S64164A Revision History Revision 0.1 23 Oct. 2006 - Original Revision 0.2 (06 Jun. 2007) - Add BGA type spec Revision 0.3 (20 Jul. 2007) - Modify BGA assignment Revision 0.4 (01 Oct. 2007) - Modify IDD spec. Revision 1.0 (20 Nov. 2007) - Delete “Preliminary”


    Original     		PDF M13S64164A M13S64164A

    M13S32321A

    Abstract: No abstract text available
    Text: ESMT M13S32321A DDR SDRAM 256K x 32 Bit x 4 Banks Double Data Rate SDRAM Features z JEDEC Standard z Internal pipelined double-data-rate architecture, two data access per clock cycle z Bi-directional data strobe DQS z On-chip DLL z Differential clock inputs (CLK and CLK )


    Original     		PDF M13S32321A M13S32321A

    M13S128324A-5BG

    Abstract: M13S128324A
    Text: ESMT M13S128324A DDR SDRAM 1M x 32 Bit x 4 Banks Double Data Rate SDRAM Features z JEDEC Standard z Internal pipelined double-data-rate architecture, two data access per clock cycle z Bi-directional data strobe DQS z On-chip DLL z Differential clock inputs (CLK and CLK )


    Original     		PDF M13S128324A M13S128324A-5BG M13S128324A

    Untitled

    Abstract: No abstract text available
    Text: ESM T M13S2561616A 2K DDR SDRAM 4M x 16 Bit x 4 Banks Double Data Rate SDRAM Features Double-data-rate architecture, two data transfers per clock cycle Bi-directional data strobe (DQS) Differential clock inputs (CLK and CLK ) DLL aligns DQ and DQS transition with CLK transition


    Original     		PDF M13S2561616A

    Untitled

    Abstract: No abstract text available
    Text: ESM T M13S128324A 2M DDR SDRAM 1M x 32 Bit x 4 Banks Double Data Rate SDRAM Features Double-data-rate architecture, two data transfers per clock cycle Bi-directional data strobe (DQS) Differential clock inputs (CLK and CLK ) DLL aligns DQ and DQS transition with CLK transition


    Original     		PDF M13S128324A

    Untitled

    Abstract: No abstract text available
    Text: ESM T M13S64164A 2Y DDR SDRAM 1M x 16 Bit x 4 Banks Double Data Rate SDRAM Features Double-data-rate architecture, two data transfers per clock cycle Bi-directional data strobe (DQS) Differential clock inputs (CLK and CLK ) DLL aligns DQ and DQS transition with CLK transition


    Original     		PDF M13S64164A

    Untitled

    Abstract: No abstract text available
    Text: ESM T M13S2561616A 2A Automotive Grade DDR SDRAM 4M x 16 Bit x 4 Banks Double Data Rate SDRAM Features Double-data-rate architecture, two data transfers per clock cycle Bi-directional data strobe (DQS) Differential clock inputs (CLK and CLK ) DLL aligns DQ and DQS transition with CLK transition


    Original     		PDF M13S2561616A

    Untitled

    Abstract: No abstract text available
    Text: ESM T M13S128168A 2N Operation Temperature Condition -40°C~85°C DDR SDRAM 2M x 16 Bit x 4 Banks Double Data Rate SDRAM Features Double-data-rate architecture, two data transfers per clock cycle Bi-directional data strobe (DQS) Differential clock inputs (CLK and CLK )


    Original     		PDF M13S128168A

    cke02

    Abstract: 100L
    Text: ESMT M13S64322A Preliminary Revision History Revision 0.5 May 03, 2007 - Delete BGA ball name of packing dimensions Revision 0.4 (May 14,2002) - Change AC Parameters Revision Rev. 0.3 Rev. 0.4 Version -4 -5 -4 -5 tRC 13 tCK 11 tCK 14 tCK 12 tCK tRP 4 tCK


    Original     		PDF M13S64322A cke02 100L

    esmt m13s2561616a

    Abstract: M13S2561616A -5T M13S2561616A
    Text: ESMT M13S2561616A Operation Temperature Condition -40~85°C Revision History Revision1.0 19 Oct. 2007 - Original Revision1.1 (06 Dec. 2007) - Add BGA package Elite Semiconductor Memory Technology Inc. Publication Date : Dec. 2007 Revision : 1.1 1/49 ESMT


    Original     		PDF M13S2561616A esmt m13s2561616a M13S2561616A -5T M13S2561616A

    M13S128324A

    Abstract: No abstract text available
    Text: ESMT M13S128324A Operation Temperature Condition -40~85°C Revision History Revision 1.0 Dec. 14 2007 -Original Elite Semiconductor Memory Technology Inc. Publication Date : Dec. 2007 Revision : 1.0 1/49 ESMT M13S128324A Operation Temperature Condition -40~85°C


    Original     		PDF M13S128324A M13S128324A

    CKE 2009

    Abstract: M13S64164A CL301
    Text: ESMT M13S64164A Operation Temperature Condition -40°C~85°C DDR SDRAM 1M x 16 Bit x 4 Banks Double Data Rate SDRAM Features z JEDEC Standard z Internal pipelined double-data-rate architecture, two data access per clock cycle z Bi-directional data strobe DQS


    Original     		PDF M13S64164A CKE 2009 M13S64164A CL301

    Untitled

    Abstract: No abstract text available
    Text: ESMT M13S128168A Revision History Revision 0.1 15 Jan. 2002 - Original Revision 0.2 (19 Nov. 2002) -changed ordering information & DC/AC characteristics Revision 0.1 Revision 0.2 M13S128168A - 5T M13S128168A - 6T M13S128168A - 6T M13S128168A - 7.5AB Revision 0.3 (8 Aug. 2003)


    Original     		PDF M13S128168A M13S128168A

    Untitled

    Abstract: No abstract text available
    Text: ESMT Prelinminary M13S2561616A Revision History Revision 0.1 28 Apr. 2006 - Original Elite Semiconductor Memory Technology Inc. Publication Date : Apr. 2006 Revision : 0.1 1/48 ESMT Prelinminary DDR SDRAM M13S2561616A 2M x 16 Bit x 4 Banks Double Data Rate SDRAM


    Original     		PDF M13S2561616A

    M13S2561616A -5T

    Abstract: M13S2561616A esmt m13s2561616a
    Text: ESMT M13S2561616A Revision History Revision 0.1 28 Apr. 2006 - Original Revision 1.0 (07 Jun. 2006) - Delete Preliminary at ever page - Revise typing error of page1 Revision 1.1 (09 May. 2007) - Modify PD, DC specifications and MRS Revision 1.2 (12 Jun. 2007)


    Original     		PDF M13S2561616A M13S2561616A -5T M13S2561616A esmt m13s2561616a

    Untitled

    Abstract: No abstract text available
    Text: ESMT M13S128168A Operation temperature condition -40°C~85°C Revision History Revision 1.0 03 Jan. 2007 - Original Elite Semiconductor Memory Technology Inc. Publication Date : Jan. 2007 Revision : 1.0 1/48 ESMT M13S128168A Operation temperature condition -40°C~85°C


    Original     		PDF M13S128168A

    Untitled

    Abstract: No abstract text available
    Text: ESMT M13S64164A DDR SDRAM 1M x 16 Bit x 4 Banks Double Data Rate SDRAM Features z JEDEC Standard z Internal pipelined double-data-rate architecture, two data access per clock cycle z Bi-directional data strobe DQS z On-chip DLL z Differential clock inputs (CLK and CLK )


    Original     		PDF M13S64164A

    M13S256328A

    Abstract: No abstract text available
    Text: ESMT M13S256328A DDR SDRAM 2M x 32 Bit x 4 Banks Double Data Rate SDRAM Features z JEDEC Standard z Internal pipelined double-data-rate architecture, two data access per clock cycle z Bi-directional data strobe DQS z On-chip DLL z Differential clock inputs (CLK and CLK )


    Original     		PDF M13S256328A M13S256328A

    M13S64164A

    Abstract: No abstract text available
    Text: ESMT Preliminary M13S64164A Revision History Revision 0.1 23 Oct. 2006 - Original Revision 0.2 (06 Jun. 2007) - Add BGA type spec Revision 0.3 (20 Jul. 2007) - Modify BGA assignment Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007


    Original     		PDF M13S64164A M13S64164A

    Untitled

    Abstract: No abstract text available
    Text: ESMT Preliminary M13S128168A Revision History Revision 0.1 15 Jan. 2002 - Original Revision 0.2 (19 Nov. 2002) -changed ordering information & DC/AC characteristics Revision 0.1 Revision 0.2 M13S128168A - 5T M13S128168A - 6T M13S128168A - 6T M13S128168A - 7.5AB


    Original     		PDF M13S128168A M13S128168A

    Untitled

    Abstract: No abstract text available
    Text: ESM T M13S128324A 2M Operation Temperature Condition -40°C~85°C DDR SDRAM 1M x 32 Bit x 4 Banks Double Data Rate SDRAM Features Double-data-rate architecture, two data transfers per clock cycle Bi-directional data strobe (DQS) Differential clock inputs (CLK and CLK )


    Original     		PDF M13S128324A

    Untitled

    Abstract: No abstract text available
    Text: ESM T M13S128168A 2N Automotive Grade DDR SDRAM 2M x 16 Bit x 4 Banks Double Data Rate SDRAM Features  Double-data-rate architecture, two data transfers per clock cycle  Bi-directional data strobe (DQS)  Differential clock inputs (CLK and CLK )


    Original     		PDF M13S128168A