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    LVDS REGISTER Search Results

    LVDS REGISTER Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    SF-10GSFPPLCL-000 Amphenol Cables on Demand Amphenol SF-10GSFPPLCL-000 SFP+ Optical Module - 10GBASE-SR (up to 300m/984') SFP+ Multimode Optical Transceiver Module (Duplex LC Connectors) - Cisco & HP Compatible Datasheet
    SF-XP85B102DX-000 Amphenol Cables on Demand Amphenol SF-XP85B102DX-000 SFP28 25GBASE-SR Short-Range 850nm Multi-Mode Optical Transceiver Module (Duplex LC Connector) by Amphenol XGIGA [XP85B102DX] Datasheet
    SF-QXP85B402D-000 Amphenol Cables on Demand Amphenol SF-QXP85B402D-000 QSFP28 100GBASE-SR Short-Range 850nm Multi-Mode Optical Transceiver Module (MTP/MPO Connector) by Amphenol XGIGA [QXP85B402D] Datasheet
    MM54HC646J/883 Rochester Electronics LLC Registered Bus Transceiver, Visit Rochester Electronics LLC Buy
    54F646/Q3A Rochester Electronics LLC 54F646 - BUS TRANSCEIVER/REGISTER Visit Rochester Electronics LLC Buy

    LVDS REGISTER Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    SCAN50C400

    Abstract: SCAN50C400UT
    Text: BR4004_5GIGV2 1/9/04 1:03 PM Page 1 SCAN50C400-Quad 1.25/2.5/5.0 Gbps backplane SerDes SCLK Channel 1, 2 Bist test pattern PLL LVDS input register F I F O LVDS transmit LVDS input register F I F O LVDS recieve LVDS output register F I F O LVDS transmit Serializer


    Original     		PDF BR4004 SCAN50C400-Quad SCAN50C400 SCAN50C400UT 25G/2 EVM50C400 SCAN50C400UT

    Untitled

    Abstract: No abstract text available
    Text: DS90LV001 DS90LV001 800 Mbps LVDS Buffer Literature Number: SNLS067D DS90LV001 800 Mbps LVDS Buffer General Description The DS90LV001 LVDS-LVDS Buffer takes an LVDS input signal and provides an LVDS output signal. In many large systems, signals are distributed across backplanes, and one


    Original     		PDF DS90LV001 DS90LV001 SNLS067D DS90/clocks

    MAX9174

    Abstract: MAX9174ETB MAX9174EUB MAX9175 MAX9175ETB MAX9175EUB MAX9176
    Text: 19-2827; Rev 0; 4/03 670MHz LVDS-to-LVDS and Anything-to-LVDS 1:2 Splitters Features ♦ 1.0ps RMS Jitter (max) at 670MHz The MAX9174 has a fail-safe LVDS input and LVDS outputs. The MAX9175 has an anything differential input (CML/LVDS/LVPECL) and LVDS outputs. The outputs


    Original     		PDF 670MHz 670MHz MAX9174 MAX9175 MAX9175 MAX9174/MAX9175 MO229 MAX9174ETB MAX9174EUB MAX9175ETB MAX9175EUB MAX9176

    Untitled

    Abstract: No abstract text available
    Text: 19-2757; Rev 0; 1/03 670MHz LVDS-to-LVDS and Anything-to-LVDS 2:1 Multiplexers Features ♦ 1.0ps RMS Jitter (max) at 670MHz The MAX9176 has fail-safe LVDS inputs and an LVDS output. The MAX9177 has “anything” differential inputs (CML/LVDS/LVPECL) and an LVDS output. The output


    Original     		PDF 670MHz 670MHz MAX9176 MAX9177 MAX9177 MAX9177) MO229 T1033-1

    MAX9176

    Abstract: No abstract text available
    Text: 19-2757; Rev 0; 1/03 670MHz LVDS-to-LVDS and Anything-to-LVDS 2:1 Multiplexers Features ♦ 1.0ps RMS Jitter (max) at 670MHz The MAX9176 has fail-safe LVDS inputs and an LVDS output. The MAX9177 has “anything” differential inputs (CML/LVDS/LVPECL) and an LVDS output. The output


    Original     		PDF 670MHz 670MHz MAX9176 MAX9177 MAX9177 MAX9177) MO229 T1033-1

    DS91C176

    Abstract: DS91C176TMA DS91D176 DS91D176TMA M08A 1200V
    Text: DS91D176/DS91C176 Multipoint-LVDS M-LVDS Transceivers General Description The DS91C176 and DS91D176 are high-speed M-LVDS differential transceivers designed for multipoint applications with multiple drivers or receivers. Multipoint LVDS (M-LVDS) is a new bus interface standard (TIA/EIA-899) based on LVDS but


    Original     		PDF DS91D176/DS91C176 DS91C176 DS91D176 TIA/EIA-899) DS91C176TMA DS91D176TMA M08A 1200V

    sublvds to lvds

    Abstract: sublvds sub-lvds TN1210 sublvds lvds c2 sub HSTL18D
    Text: Sub-LVDS Signaling Using Lattice Devices July 2010 Technical Note TN1210 Introduction Sub-LVDS is a reduced-voltage form of LVDS signaling, very similar to LVDS. Being similar to LVDS, Lattice FPGA devices can support the sub-LVDS signaling with other differential I/O standards already supported as part of the


    Original     		PDF TN1210 SSTL18D 1-800-LATTICE sublvds to lvds sublvds sub-lvds TN1210 sublvds lvds c2 sub HSTL18D

    Untitled

    Abstract: No abstract text available
    Text: MAX9376 LVDS/Anything-to-LVPECL/LVDS Dual Translator General Description The MAX9376 is a fully differential, high-speed, LVDS/ anything-to-LVPECL/LVDS dual translator designed for signal rates up to 2GHz. One channel is LVDS/ anything-to-LVPECL translator and the other channel


    Original     		PDF MAX9376 MAX9376 MAX9376â 100mV.

    Untitled

    Abstract: No abstract text available
    Text: 19-2809; Rev 1; 10/09 LVDS/Anything-to-LVPECL/LVDS Dual Translator The MAX9376 is a fully differential, high-speed, LVDS/anything-to-LVPECL/LVDS dual translator designed for signal rates up to 2GHz. One channel is LVDS/anything-to-LVPECL translator and the other


    Original     		PDF MAX9376 MAX9376â 100mV. MAX9376

    JESD51-7

    Abstract: MAX9376 MAX9376EUB 630ps
    Text: 19-2809; Rev 1; 10/09 LVDS/Anything-to-LVPECL/LVDS Dual Translator The MAX9376 is a fully differential, high-speed, LVDS/anything-to-LVPECL/LVDS dual translator designed for signal rates up to 2GHz. One channel is LVDS/anything-to-LVPECL translator and the other


    Original     		PDF MAX9376 100mV. MAX9376 JESD51-7 MAX9376EUB 630ps

    M08A

    Abstract: DS90LV001 DS90LV001TLD DS90LV001TM
    Text: DS90LV001 800 Mbps LVDS Buffer General Description The DS90LV001 LVDS-LVDS Buffer takes an LVDS input signal and provides an LVDS output signal. In many large systems, signals are distributed across backplanes, and one of the limiting factors for system speed is the "stub length" or


    Original     		PDF DS90LV001 DS90LV001 DS90LV001, M08A DS90LV001TLD DS90LV001TM

    LVDS Cable STP

    Abstract: AEC-Q100 DS90C124 DS90C365A DS90UR124 DS90UR241 DS99R421 ISO10605 RGB666
    Text: DS99R421 5-43 MHz FPD-Link LVDS 3 Data + 1 Clock to Single Embedded Clock DC-Balanced LVDS Converter General Description Features The DS99R421 converts a FPD-Link input with 4 non-DC Balanced LVDS (3 LVDS Data + LVDS Clock) plus 3 oversampled low speed control bits into a single LVDS DC-balanced serial stream with embedded clock information. This


    Original     		PDF DS99R421 DS99R421 24-bit LVDS Cable STP AEC-Q100 DS90C124 DS90C365A DS90UR124 DS90UR241 ISO10605 RGB666

    40 pin lvds converter

    Abstract: AEC-Q100 DS90C124 DS90C365A DS90UR124 DS90UR241 DS99R421 ISO10605 RGB666 LVDS SERIALIZER SWITCHING NOISE SUPPRESSION
    Text: DS99R421 5-43 MHz FPD-Link LVDS 3 Data + 1 Clock to Single Embedded Clock DC-Balanced LVDS Converter General Description Features The DS99R421 converts a FPD-Link input with 4 non-DC Balanced LVDS (3 LVDS Data + LVDS Clock) plus 3 oversampled low speed control bits into a single LVDS DC-balanced serial stream with embedded clock information. This


    Original     		PDF DS99R421 DS99R421 24-bit 40 pin lvds converter AEC-Q100 DS90C124 DS90C365A DS90UR124 DS90UR241 ISO10605 RGB666 LVDS SERIALIZER SWITCHING NOISE SUPPRESSION

    Untitled

    Abstract: No abstract text available
    Text: PRELIMINARY ICS844003 FEMTOCLOCKS CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER GENERAL DESCRIPTION FEATURES • Three LVDS outputs on two banks, A Bank with one LVDS pair and B Bank with 2 LVDS output pairs The ICS844003 is a 3 differential output LVDS Synthesizer designed to generate Ethernet reference


    Original     		PDF ICS844003 ICS844003 25MHz 041666MHz, 625MHz, 25MHz, 125MHz. 199707558G

    Untitled

    Abstract: No abstract text available
    Text: PRELIMINARY ICS844003 FEMTOCLOCKS CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER GENERAL DESCRIPTION FEATURES • Three LVDS outputs on two banks, A Bank with one LVDS pair and B Bank with 2 LVDS output pairs The ICS844003 is a 3 differential output LVDS Synthesizer designed to generate Ethernet reference


    Original     		PDF ICS844003 ICS844003 25MHz 041666MHz, 625MHz, 25MHz, 125MHz. 199707558G

    DS91M125TMA

    Abstract: M16A SOIC-16
    Text: DS91M125 125 MHz 1:4 M-LVDS Repeater with LVDS Input General Description Features The DS91M125 is a 1:4 M-LVDS repeater designed for driving and distributing clock or data signals to up to four multipoint networks. M-LVDS Multipoint LVDS is a new family of bus interface


    Original     		PDF DS91M125 DS91M125 DS91M125TMA M16A SOIC-16

    DS90UR124

    Abstract: AEC-Q100 DS90C124 DS90C365A DS90UR241 DS99R421 ISO10605 RGB666 300113
    Text: DS99R421 5-43 MHz FPD-Link LVDS 3 Data + 1 Clock to FPD-Link II LVDS (Embedded Clock DC-Balanced) Converter General Description Features The DS99R421 converts a FPD-Link input with 4 non-DC Balanced LVDS (3 LVDS Data + LVDS Clock) plus 3 oversampled low speed control bits into a single LVDS DC-balanced serial stream with embedded clock information. This


    Original     		PDF DS99R421 DS99R421 24-bit DS90UR124 AEC-Q100 DS90C124 DS90C365A DS90UR241 ISO10605 RGB666 300113

    AEC-Q100

    Abstract: DS90C124 DS90C365A DS90UR124 DS90UR241 DS99R421 ISO10605 RGB666
    Text: DS99R421 5-43 MHz FPD-Link LVDS 3 Data + 1 Clock to Single Embedded Clock DC-Balanced LVDS Converter General Description Features The DS99R421 converts a FPD-Link input with 4 non-DC Balanced LVDS (3 LVDS Data + LVDS Clock) plus 3 oversampled low speed control bits into a single LVDS DC-balanced serial stream with embedded clock information. This


    Original     		PDF DS99R421 DS99R421 24-bit AEC-Q100 DS90C124 DS90C365A DS90UR124 DS90UR241 ISO10605 RGB666

    Untitled

    Abstract: No abstract text available
    Text: August 8, 2008 DS91M125 125 MHz 1:4 M-LVDS Repeater with LVDS Input General Description Features The DS91M125 is a 1:4 M-LVDS repeater designed for driving and distributing clock or data signals to up to four multipoint networks. M-LVDS Multipoint LVDS is a new family of bus interface


    Original     		PDF DS91M125 DS91M12ductor

    Untitled

    Abstract: No abstract text available
    Text: DS91M125 DS91M125 125 MHz 1:4 M-LVDS Repeater with LVDS Input Literature Number: SNLS290B DS91M125 125 MHz 1:4 M-LVDS Repeater with LVDS Input General Description Features The DS91M125 is a 1:4 M-LVDS repeater designed for driving and distributing clock or data signals to up to four multipoint networks.


    Original     		PDF DS91M125 DS91M125 SNLS290B

    lvds pinout

    Abstract: LVDS DISPLAY 20 pin us8 Package FAIRCHILD TSSOP-48 maxim cross reference DS90CR218 FIN1002 SN64LVDS95 DS90C385 FIN1001
    Text: Analog Discrete Interface & Logic Optoelectronics LVDS: High-Performance Point-to-Point Solutions LVDS: High-Performance Point-to-Point Solutions LVDS Technology LVDS is a low-power, low-noise differential technology for high speed transmission. Optimized for point-to-point interconnect


    Original     		PDF Power247TM, lvds pinout LVDS DISPLAY 20 pin us8 Package FAIRCHILD TSSOP-48 maxim cross reference DS90CR218 FIN1002 SN64LVDS95 DS90C385 FIN1001

    lvds 40 pin pinout

    Abstract: Integrated Device Technology CROSS
    Text: Freescale Semiconductor, Inc. Order number: MC100ES7011H 0, 05/2004 DATARevSHEET TECHNICAL DATA Product Preview MC100ES7011H Low Voltage 1:2 Differential HSTL/LVDS-to-LVDS Clock MC100ES7011H Fanout Buffer The MC100ES7011H is a low voltage 1:2 Differential HSTL/LVDS to LVDS


    Original     		PDF MC100ES7011H 199707558G lvds 40 pin pinout Integrated Device Technology CROSS

    RS-485 spice

    Abstract: RS-422 spice RS644 comparison RS485 to RS644 FIN51021 FIN1017 FIN1018 FIN1019 FIN1027 FIN1028
    Text: LVDS High-Performance Point-to-Point Solutions Product Overview Low Voltage Differential Signaling LVDS technology delivers high-speed data transmission between • Cards • Racks • Backplanes • Cabinets LVDS Technology LVDS is a low-power, low-noise differential technology


    Original     		PDF RS-422 RS-485 RS-485 spice RS-422 spice RS644 comparison RS485 to RS644 FIN51021 FIN1017 FIN1018 FIN1019 FIN1027 FIN1028

    AN1568

    Abstract: DL140 MC100EL17 MC100LVEL17 MC100LVEL39 MC100LVEL90 P1596 DL140-D Nippon capacitors
    Text: AN1568 Application Note Interfacing Between LVDS and ECL Prepared by Andrea Diermeier Motorola Logic Engineering 5/96  Motorola, Inc. 1996 5–1 REV 0 AN1568 Interfacing Between LVDS and ECL Introduction LVDS Levels LVDS Low Voltage Differential Signaling signals are


    Original     		PDF AN1568 DL140 AN1568/D* AN1568/D AN1568 MC100EL17 MC100LVEL17 MC100LVEL39 MC100LVEL90 P1596 DL140-D Nippon capacitors