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    LVDS 20 PIN TO 30 PIN Search Results

    LVDS 20 PIN TO 30 PIN Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    CS-DSDMDB09MF-010 Amphenol Cables on Demand Amphenol CS-DSDMDB09MF-010 9-Pin (DB9) Deluxe D-Sub Cable - Copper Shielded - Male / Female 10ft Datasheet
    CS-DSDMDB15MF-002.5 Amphenol Cables on Demand Amphenol CS-DSDMDB15MF-002.5 15-Pin (DB15) Deluxe D-Sub Cable - Copper Shielded - Male / Female 2.5ft Datasheet
    CS-DSDMDB15MM-025 Amphenol Cables on Demand Amphenol CS-DSDMDB15MM-025 15-Pin (DB15) Deluxe D-Sub Cable - Copper Shielded - Male / Male 25ft Datasheet
    CS-DSDMDB25MM-010 Amphenol Cables on Demand Amphenol CS-DSDMDB25MM-010 25-Pin (DB25) Deluxe D-Sub Cable - Copper Shielded - Male / Male 10ft Datasheet
    CS-DSDMDB37MM-002.5 Amphenol Cables on Demand Amphenol CS-DSDMDB37MM-002.5 37-Pin (DB37) Deluxe D-Sub Cable - Copper Shielded - Male / Male 2.5ft Datasheet

    LVDS 20 PIN TO 30 PIN Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    Untitled

    Abstract: No abstract text available
    Text: UVVJ Series 5x7 mm, 3.3 Volt, LVPECL/LVDS, VCXO • Integrated phase jitter of less than 1 ps from 12 kHz to 20 MHz • Ideal for 10 and 40 Gigabit Ethernet and Optical Carrier applications Pin Connections 30 UVVJ Series 5x7 mm, 3.3 Volt, LVPECL/LVDS, VCXO


    Original     		PDF

    top mark QA1

    Abstract: ICS843S2807 ICS843S2807BY MS-026 Nippon capacitors
    Text: PRELIMINARY ICS843S2807 FEMTOCLOCK CRYSTAL-TOLVPECL/LVDS/LVCMOS CLOCK GENERATOR • Maximum output frequency: 350MHz VCCO_LVCMOS QA0 VEE QB1 • Crystal input frequency: 25MHz QB0 PIN ASSIGNMENT VCCO_LVCMOS • Five banks of outputs: Bank A: one single-ended QA0 LVCMOS output at: 133MHz


    Original     		PDF ICS843S2807 350MHz 25MHz 133MHz 67MHz, 100MHz 125MHz 50MHz top mark QA1 ICS843S2807 ICS843S2807BY MS-026 Nippon capacitors

    Untitled

    Abstract: No abstract text available
    Text: V386 8-BIT LVDS RECEIVER FOR VIDEO General Description Features The V386 is an ideal LVDS receiver that converts 4-pair LVDS data streams into parallel 28 bits of CMOS/TTL data with bandwidth up to 2.38 Gbps throughput or 297.5 Mbytes per second. • Pin and function compatible with the National


    Original     		PDF DS90CF386, THC63LVDF84, SN65LVDS94 RxOUT22 RxOUT23 RxOUT24

    SN65LVDS1224

    Abstract: LVDS Serializer MO-150 SN65LV1023 SN65LV1023DB SN65LV1224 SN65LV1224DB SN65LVDS1023
    Text: SN65LV1023/SN65LV1224† 30 MHz TO 66 MHz, 10:1 LVDS SERIALIZER/DESERIALIZER SLLS527B – FEBRUARY 2002 – REVISED APRIL 2002 D D D D 300–660 Mbps Serial LVDS Data Payload Bandwidth at 30 MHz to 66 MHz System Clock Pin-Compatible Superset of NSM DS92LV1023/DS92LV1224


    Original     		PDF SN65LV1023/SN65LV1224 SLLS527B DS92LV1023/DS92LV1224 28-Pin SN65LV1023 SN65LVDS1224 LVDS Serializer MO-150 SN65LV1023 SN65LV1023DB SN65LV1224 SN65LV1224DB SN65LVDS1023

    Untitled

    Abstract: No abstract text available
    Text: SN65LV1023/SN65LV1224† 30 MHz TO 66 MHz, 10:1 LVDS SERIALIZER/DESERIALIZER SLLS527C – FEBRUARY 2002 – REVISED MAY 2002 D D D D 300–660 Mbps Serial LVDS Data Payload Bandwidth at 30 MHz to 66 MHz System Clock Pin-Compatible Superset of NSM DS92LV1023/DS92LV1224


    Original     		PDF SN65LV1023/SN65LV1224 SLLS527C DS92LV1023/DS92LV1224 SN65LV1023 28-Pin SN65LV1224

    metal detector plans

    Abstract: SI5334A Si5334C-Axxxxx-GM JESD78 Si5334 SSTL-18 Si5334B-Axxxxx-GM SI5334D
    Text: Si5334 P I N - C ONTR OLLED A N Y - F REQUENCY, A NY - O UTPUT Q U A D C L O C K G ENERATOR Features Applications Si5334 Transparent Top View OEB  Pin Assignments VDDO0  Ordering Information: See page 24. CLK0B  CLK0A  Independent output voltage per


    Original     		PDF Si5334 24-QFN metal detector plans SI5334A Si5334C-Axxxxx-GM JESD78 Si5334 SSTL-18 Si5334B-Axxxxx-GM SI5334D

    DS15BR400

    Abstract: AN1194 DS15BR400EVK DS15BR401 TQFP-48
    Text: DS15BR400/DS15BR401 4-Channel LVDS Buffer/Repeater with Pre-Emphasis General Description Features The DS15BR400/DS15BR401 are four channel LVDS buffer/ repeaters capable of datarates of up to 2 Gbps. High speed data paths and flow-through pinout minimize internal device


    Original     		PDF DS15BR400/DS15BR401 DS15BR400/DS15BR401 DS15BR400 DS15BR401 AN1194 DS15BR400EVK TQFP-48

    DS15BR400

    Abstract: DS15BR400EVK AN-1194 DS15BR401 TQFP-48
    Text: DS15BR400/DS15BR401 4-Channel LVDS Buffer/Repeater with Pre-Emphasis General Description Features The DS15BR400/DS15BR401 are four channel LVDS buffer/ repeaters capable of datarates of up to 2 Gbps. High speed data paths and flow-through pinout minimize internal device


    Original     		PDF DS15BR400/DS15BR401 DS15BR400/DS15BR401 DS15BR400 DS15BR401 DS15BR400EVK AN-1194 TQFP-48

    Untitled

    Abstract: No abstract text available
    Text: SN65LV1023/SN65LV1224 30 MHz TO 66 MHz, 10:1 LVDS SERIALIZER/DESERIALIZER SLLS527A – FEBRUARY 2002 – REVISED APRIL 2002 D D D D 300–660 Mbps Serial LVDS Data Payload Bandwidth at 30 MHz to 66 MHz System Clock Pin-Compatible Superset of NSM DS92LV1023/DS92LV1224


    Original     		PDF SN65LV1023/SN65LV1224 SLLS527A DS92LV1023/DS92LV1224 SN65LV1023 28-Pin SN65LV1224

    DS15BR400

    Abstract: AN-1194 DS15BR400EVK DS15BR401 TQFP-48
    Text: DS15BR400/DS15BR401 4-Channel LVDS Buffer/Repeater with Pre-Emphasis General Description Features The DS15BR400/DS15BR401 are four channel LVDS buffer/ repeaters capable of datarates of up to 2 Gbps. High speed data paths and flow-through pinout minimize internal device


    Original     		PDF DS15BR400/DS15BR401 DS15BR400/DS15BR401 DS15BR400 DS15BR401 AN-1194 DS15BR400EVK TQFP-48

    Untitled

    Abstract: No abstract text available
    Text: 19-2392; Rev 0; 4/02 LVDS or LVTTL/LVCMOS Input to 14 LVTTL/LVCMOS Output Clock Driver Features ♦ LVDS or LVTTL/LVCMOS Input Selection The MAX9160 is designed to operate with a 3.3V supply voltage over the extended temperature range of -40°C to +85°C. This device is available in 28-pin


    Original     		PDF MAX9160 28-pin 32-lead 125MHz 200ps 100ps 125MHz MAX9160

    DS15BR400

    Abstract: AN-1194 DS15BR400EVK DS15BR401 TQFP-48
    Text: DS15BR400/DS15BR401 4-Channel LVDS Buffer/Repeater with Pre-Emphasis General Description Features The DS15BR400/DS15BR401 are four channel LVDS buffer/ repeaters capable of datarates of up to 2 Gbps. High speed data paths and flow-through pinout minimize internal device


    Original     		PDF DS15BR400/DS15BR401 DS15BR400/DS15BR401 DS15BR400 DS15BR401 AN-1194 DS15BR400EVK TQFP-48

    Untitled

    Abstract: No abstract text available
    Text: ZL40220 Precision 2:6 LVDS Fanout Buffer with Glitch-free Input Reference Switching Data Sheet November 2012 Features Ordering Information ZL40220LDG1 32 Pin QFN Trays ZL40220LDF1 32 Pin QFN Tape and Reel Inputs/Outputs • Accepts two differential or single-ended inputs


    Original     		PDF ZL40220 ZL40220LDG1 ZL40220LDF1 -40oC

    MO-150

    Abstract: SN65LV1023 SN65LV1023DB SN65LV1224 SN65LV1224DB SN65LVDS1023 SN65LVDS1224
    Text: SN65LV1023/SN65LV1224 30ĆMHz TO 66ĆMHz, 10:1 LVDS SERIALIZER/DESERIALIZER SLLS527G − FEBRUARY 2002 − REVISED JANUARY 2005 D 300-Mbps to 660-Mbps Serial LVDS Data D D D Payload Bandwidth at 30-MHz to 66-MHz System Clock Pin-Compatible Superset of NSM


    Original     		PDF SN65LV1023/SN65LV1224 30MHz 66MHz, SLLS527G 300-Mbps 660-Mbps 30-MHz 66-MHz DS92LV1023/DS92LV1224 28-Pin MO-150 SN65LV1023 SN65LV1023DB SN65LV1224 SN65LV1224DB SN65LVDS1023 SN65LVDS1224

    MAX9378

    Abstract: MAX9377 MAX9377EUA MAX9378EUA
    Text: 19-2846; Rev 1; 7/03 Anything-to-LVPECL/LVDS Translators with Pin-Selectable Divide-by-Four Features ♦ Guaranteed 2GHz Switching Frequency ♦ Accept LVDS/LVPECL/Anything Inputs ♦ Pin-Selectable Divide-by-Four Function ♦ 421ps typ Propagation Delays (MAX9377)


    Original     		PDF 421ps MAX9377) 100mV MAX9377EUA MAX9378EUA MAX9377/MAX9378 MAX9378 MAX9377 MAX9377EUA MAX9378EUA

    Untitled

    Abstract: No abstract text available
    Text: 19-2846; Rev 1; 7/03 Anything-to-LVPECL/LVDS Translators with Pin-Selectable Divide-by-Four The MAX9377/MAX9378 accept any differential input signal within the supply rails and with minimum amplitude of 100mV. Inputs are fully compatible with the LVDS, LVPECL, HSTL, and CML differential signaling


    Original     		PDF MAX9377/MAX9378 100mV. MAX9377 MAX9378 EIA/TIA-644 MAX9377/MAX9378

    the pll 2002

    Abstract: No abstract text available
    Text: SN65LV1023/SN65LV1224 30-MHz TO 66-MHz, 10:1 LVDS SERIALIZER/DESERIALIZER SLLS527E – FEBRUARY 2002 – REVISED SEPTEMBER 2002 D D D D 300-Mbps to 660-Mbps Serial LVDS Data Payload Bandwidth at 30-MHz to 66-MHz System Clock Pin-Compatible Superset of NSM


    Original     		PDF SN65LV1023/SN65LV1224 30-MHz 66-MHz, SLLS527E 300-Mbps 660-Mbps 66-MHz DS92LV1023/DS92LV1224 SN65LV1023 the pll 2002

    Untitled

    Abstract: No abstract text available
    Text: V386 8-BIT LVDS RECEIVER FOR VIDEO General Description Features The V386 is an ideal LVDS receiver that converts 4-pair LVDS data streams into parallel 28 bits of CMOS/TTL data with bandwidth up to 2.38 Gbps throughput or 297.5 Mbytes per second. • Packaged in a 56-pin TSSOP Pb free available


    Original     		PDF 56-pin

    Untitled

    Abstract: No abstract text available
    Text: ZL40220 Precision 2:6 LVDS Fanout Buffer with Glitch-free Input Reference Switching Data Sheet February 2013 Features Ordering Information ZL40220LDG1 32 Pin QFN Trays ZL40220LDF1 32 Pin QFN Tape and Reel Inputs/Outputs • Accepts two differential or single-ended inputs


    Original     		PDF ZL40220 ZL40220LDG1 ZL40220LDF1 -40oC

    3 pin preset resistor 10k

    Abstract: yx 805 YX 805 4 pin C 3686 ad9550 MO-220-WHHD GPON 77.76 FRAME GR-253-CORE JESD51-2 CP2121
    Text: Integer-N Clock Translator for Wireline Communications AD9550 FEATURES BASIC BLOCK DIAGRAM REF PLL OUTPUT CIRCUITRY OUT2 OUT1 PIN DECODER AD9550 09057-001 Converts preset standard input frequencies to standard output frequencies Input frequencies from 8 kHz to 200 MHz


    Original     		PDF AD9550 GR-253-CORE 32-Lead CP-32-7) AD9550BCPZ AD9550BCPZ-REEL7 AD9550/PCBZ 3 pin preset resistor 10k yx 805 YX 805 4 pin C 3686 ad9550 MO-220-WHHD GPON 77.76 FRAME JESD51-2 CP2121

    Untitled

    Abstract: No abstract text available
    Text: SN65LV1023/SN65LV1224 30-MHz TO 66-MHz, 10:1 LVDS SERIALIZER/DESERIALIZER SLLS527D – FEBRUARY 2002 – REVISED AUGUST 2002 D D D D 300-Mbps to 660-Mbps Serial LVDS Data Payload Bandwidth at 30-MHz to 66-MHz System Clock Pin-Compatible Superset of NSM DS92LV1023/DS92LV1224


    Original     		PDF SN65LV1023/SN65LV1224 30-MHz 66-MHz, SLLS527D 300-Mbps 660-Mbps 66-MHz DS92LV1023/DS92LV1224 SN65LV1023

    Untitled

    Abstract: No abstract text available
    Text: SN65LV1023/SN65LV1224 30-MHz TO 66-MHz, 10:1 LVDS SERIALIZER/DESERIALIZER SLLS527D – FEBRUARY 2002 – REVISED AUGUST 2002 D D D D 300-Mbps to 660-Mbps Serial LVDS Data Payload Bandwidth at 30-MHz to 66-MHz System Clock Pin-Compatible Superset of NSM DS92LV1023/DS92LV1224


    Original     		PDF SN65LV1023/SN65LV1224 30-MHz 66-MHz, SLLS527D 300-Mbps 660-Mbps 66-MHz DS92LV1023/DS92LV1224 SN65LV1023

    Untitled

    Abstract: No abstract text available
    Text: Integer-N Clock Translator for Wireline Communications AD9550 FEATURES BASIC BLOCK DIAGRAM REF PLL OUTPUT CIRCUITRY OUT2 OUT1 PIN DECODER AD9550 09057-001 Converts preset standard input frequencies to standard output frequencies Input frequencies from 8 kHz to 200 MHz


    Original     		PDF AD9550 GR-253-CORE 32-Lead CP-32-7) AD9550BCPZ AD9550BCPZ-REEL7 AD9550/PCBZ

    MAX9110

    Abstract: MAX9112 MAX9159 MAX9159ESA SN65LVDS9637 "DUAL LVDS"
    Text: 19-2274; Rev 0; 1/02 Dual LVDS Line Receiver Features ♦ Pin Compatible with SN65LVDS9637 ♦ Fail-Safe Circuit Sets Output High for Undriven Inputs ♦ Conforms to ANSI TIA/EIA-644 Standard ♦ Single 3.3V Supply ♦ Designed for Data Rates up to 400Mbps


    Original     		PDF SN65LVDS9637 TIA/EIA-644 400Mbps 100mV 200MHz MAX9159ESA MAX9159 MAX9110 MAX9112 MAX9159 MAX9159ESA SN65LVDS9637 "DUAL LVDS"