2DL15
Abstract: CY2DL15110
Text: CY2DL15110 1:10 Differential LVDS Fanout Buffer with Selectable Clock Input 1:10 Differential LVDS Fanout Buffer with Selectable Clock Input Features Functional Description • Select one of two low-voltage differential signal LVDS input pairs to distribute to 10 LVDS output pairs
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CY2DL15110
CY2DL15110
2DL15
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Untitled
Abstract: No abstract text available
Text: CY2DL15110 1:10 Differential LVDS Fanout Buffer with Selectable Clock Input 1:10 Differential LVDS Fanout Buffer with Selectable Clock Input Features Functional Description • Select one of two low-voltage differential signal LVDS input pairs to distribute to 10 LVDS output pairs
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CY2DL15110
40-ps
600-ps
11-ps
12-kHz
20-MHz
32-pin
CY2DL15110
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Untitled
Abstract: No abstract text available
Text: CY2DL1510 1:10 Differential LVDS Fanout Buffer 1:10 Differential LVDS Fanout Buffer Features Functional Description • Low-voltage differential signal LVDS input with on-chip 100 input termination resistor ■ Ten differential LVDS outputs ■ 40 ps maximum output-to-output skew
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CY2DL1510
32-pin
CY2DL1510
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AD941
Abstract: P2826
Text: 10-Bit, 170/200 MSPS 3.3 V A/D Converter AD9411 Data Sheet FEATURES SCALABLE REFERENCE TRACK AND HOLD ADC 10 10-BIT PIPELINE / CORE TE VIN+ AD9411 VIN– CLK+ CLK– CLOCK MANAGEMENT LVDS OUTPUTS LVDS TIMING DATA, OVERRANGE IN LVDS DCO+ DCO– S1 S5 Figure 1.
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AD9430
10-Bit,
AD9411
MS-026-AED-HD
100-Lead
SV-100)
AD9411BSVZ-170
AD9411BSVZ-200
AD941
P2826
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Untitled
Abstract: No abstract text available
Text: MOTOROLA Order Number: MC100ES7111/D Rev 0, 12/2002 SEMICONDUCTOR TECHNICAL DATA DATA SHEET Preliminary Information Low Voltage 1:10 Differential LVDS Clock Fanout Buffer Low Voltage 1:10 Differential LVDS Clock Fanout Buffer The Motorola MC100ES7111 is a LVDS differential clock fanout buffer.
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MC100ES7111/D
MC100ES7111
199707558G
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max9234eum
Abstract: MAX9234 MAX9236EUM MAX9238 marking aaa
Text: 19-3641; Rev 1; 10/07 Hot-Swappable, 21-Bit, DC-Balanced LVDS Deserializers The MAX9234/MAX9236/MAX9238 deserialize three LVDS serial-data inputs into 21 single-ended LVCMOS/LVTTL outputs. A parallel-rate LVDS clock received with the LVDS data streams provides timing for
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21-Bit,
MAX9234/MAX9236/MAX9238
MAX9209/MAX9211/
MAX9213/MAX9215
MAX9234
MAX9234/MAX9236/MAX9238
max9234eum
MAX9236EUM
MAX9238
marking aaa
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Untitled
Abstract: No abstract text available
Text: 19-3641; Rev 1; 10/07 Hot-Swappable, 21-Bit, DC-Balanced LVDS Deserializers The MAX9234/MAX9236/MAX9238 deserialize three LVDS serial-data inputs into 21 single-ended LVCMOS/LVTTL outputs. A parallel-rate LVDS clock received with the LVDS data streams provides timing for
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21-Bit,
MAX9234/MAX9236/MAX9238
MAX9209/MAX9211/
MAX9213/MAX9215
MAX9234
MAX9234/MAX9236/MAX9238
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DS92LV1023
Abstract: DS92LV1023TMSA DS92LV1224 DS92LV1224TMSA MSA28
Text: DS92LV1023 and DS92LV1224 40-66 MHz 10 Bit Bus LVDS Serializer and Deserializer General Description The DS92LV1023 transforms a 10-bit wide parallel LVCMOS/LVTTL data bus into a single high speed Bus LVDS serial data stream with embedded clock. The DS92LV1224 receives the Bus LVDS serial data stream and
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DS92LV1023
DS92LV1224
10-bit
DS92LV1224
DS92LV1023/DS92LV1224
DS92LV1023TMSA
DS92LV1224TMSA
MSA28
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Untitled
Abstract: No abstract text available
Text: DS92LV1023 and DS92LV1224 40-66 MHz 10 Bit Bus LVDS Serializer and Deserializer General Description The DS92LV1023 transforms a 10-bit wide parallel LVCMOS/LVTTL data bus into a single high speed Bus LVDS serial data stream with embedded clock. The DS92LV1224 receives the Bus LVDS serial data stream and
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DS92LV1023
DS92LV1224
10-bit
AN-1217:
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DS92LV1023
Abstract: DS92LV1023TMSA DS92LV1210 DS92LV1212 DS92LV1224 DS92LV1224TMSA MSA28
Text: DS92LV1023 and DS92LV1224 40-66 MHz 10 Bit Bus LVDS Serializer and Deserializer General Description The DS92LV1023 transforms a 10-bit wide parallel LVCMOS/LVTTL data bus into a single high speed Bus LVDS serial data stream with embedded clock. The DS92LV1224 receives the Bus LVDS serial data stream and
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DS92LV1023
DS92LV1224
10-bit
DS92LV1224
DS92LV1023TMSA
DS92LV1210
DS92LV1212
DS92LV1224TMSA
MSA28
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Untitled
Abstract: No abstract text available
Text: DS92LV1021A DS92LV1021A 16-40 MHz 10 Bit Bus LVDS Serializer Literature Number: SNLS151F DS92LV1021A 16-40 MHz 10 Bit Bus LVDS Serializer General Description The DS92LV1021A transforms a 10-bit wide parallel LVCMOS/LVTTL data bus into a single high speed Bus
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DS92LV1021A
DS92LV1021A
SNLS151F
10-bit
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SNLS151F
Abstract: SNLS151
Text: DS92LV1021A DS92LV1021A 16-40 MHz 10 Bit Bus LVDS Serializer Literature Number: SNLS151F DS92LV1021A 16-40 MHz 10 Bit Bus LVDS Serializer General Description The DS92LV1021A transforms a 10-bit wide parallel LVCMOS/LVTTL data bus into a single high speed Bus
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DS92LV1021A
DS92LV1021A
SNLS151F
10-bit
SNLS151F
SNLS151
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DS92LV1210TMSA
Abstract: No abstract text available
Text: DS92LV1021,DS92LV1210 DS92LV1021 and DS92LV1210 16-40 MHz 10 Bit Bus LVDS Serializer and Deserializer Literature Number: SNLS024B DS92LV1021 and DS92LV1210 16-40 MHz 10 Bit Bus LVDS Serializer and Deserializer General Description The DS92LV1021 transforms a 10-bit wide parallel CMOS/
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DS92LV1021
DS92LV1210
DS92LV1210
SNLS024B
DS92LV1210TMSA
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camera-link to hd-SDI converter
Abstract: QFN-64 footprint Virtex-4 serdes schematic usb to rj45 cable extender Virtex-4 uart controller datasheet usb to lvds converter camera-link to SDI converter LQFP-64 footprint schematic satellite finder dp83848 application
Text: Interface Products Selection Guide 4Q 2006 LVDS Drivers/Receivers Transceivers . 5-6 LVDS and CML PHYs Differential to Differential . 7-10 SerDes . 11-13 Serial Digital Interface
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Untitled
Abstract: No abstract text available
Text: SN65LV1023A/SN65LV1224B 10ĆMHz TO 66ĆMHz, 10:1 LVDS SERIALIZER/DESERIALIZER SLLS621B − SEPTEMBER 2004 − REVISED JULY 2005 D 100-Mbps to 660-Mbps Serial LVDS Data D D D Payload Bandwidth at 10-MHz to 66-MHz System Clock Pin-Compatible Superset of NSM
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SN65LV1023A/SN65LV1224B
10MHz
66MHz,
SLLS621B
100-Mbps
660-Mbps
10-MHz
66-MHz
DS92LV1023/DS92LV1224
28-Pin
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Untitled
Abstract: No abstract text available
Text: SN65LV1023A/SN65LV1224B 10ĆMHz TO 66ĆMHz, 10:1 LVDS SERIALIZER/DESERIALIZER SLLS621A − SEPTEMBER 2004 − REVISED JANUARY 2005 D 100-Mbps to 660-Mbps Serial LVDS Data D D D Payload Bandwidth at 10-MHz to 66-MHz System Clock Pin-Compatible Superset of NSM
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SN65LV1023A/SN65LV1224B
10MHz
66MHz,
SLLS621A
100-Mbps
660-Mbps
10-MHz
66-MHz
DS92LV1023/DS92LV1224
SN65LV1023A
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Untitled
Abstract: No abstract text available
Text: 10-Bit, 170/200 MSPS 3.3 V A/D Converter AD9411 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM SENSE VREF AGND DRGND DRVDD AVDD SCALABLE REFERENCE VIN+ VIN– CLK+ CLK– TRACK AND HOLD AD9411 ADC 10 10-BIT PIPELINE / CORE CLOCK MANAGEMENT LVDS OUTPUTS LVDS TIMING
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10-Bit,
AD9411
10-BIT
MS-026-AED-HD
21809-A
100-Lead
SV-100)
AD9411BSVZ-170
AD9411BSVZ-200
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footprint for transformer
Abstract: No abstract text available
Text: 10-Bit, 170/200 MSPS 3.3 V A/D Converter AD9411 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM SENSE VREF AGND DRGND DRVDD AVDD SCALABLE REFERENCE VIN+ VIN– CLK+ CLK– TRACK AND HOLD AD9411 ADC 10 10-BIT PIPELINE / CORE CLOCK MANAGEMENT LVDS OUTPUTS LVDS TIMING
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AD9430
10-Bit,
AD9411
10-BIT
MS-026-AED-HD
100-Lead
SV-100)
AD9411BSVZ-170
AD9411BSVZ-200
footprint for transformer
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Untitled
Abstract: No abstract text available
Text: SN65LV1023A/SN65LV1224B 10ĆMHz TO 66ĆMHz, 10:1 LVDS SERIALIZER/DESERIALIZER SLLS621A − SEPTEMBER 2004 − REVISED JANUARY 2005 D 100-Mbps to 660-Mbps Serial LVDS Data D D D Payload Bandwidth at 10-MHz to 66-MHz System Clock Pin-Compatible Superset of NSM
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SN65LV1023A/SN65LV1224B
10MHz
66MHz,
SLLS621A
100-Mbps
660-Mbps
10-MHz
66-MHz
DS92LV1023/DS92LV1224
SN65LV1023A
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Untitled
Abstract: No abstract text available
Text: SN65LV1023A/SN65LV1224B 10ĆMHz TO 66ĆMHz, 10:1 LVDS SERIALIZER/DESERIALIZER SLLS621B − SEPTEMBER 2004 − REVISED JULY 2005 D 100-Mbps to 660-Mbps Serial LVDS Data D D D Payload Bandwidth at 10-MHz to 66-MHz System Clock Pin-Compatible Superset of NSM
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SN65LV1023A/SN65LV1224B
10MHz
66MHz,
SLLS621B
100-Mbps
660-Mbps
10-MHz
66-MHz
DS92LV1023/DS92LV1224
28-Pin
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Untitled
Abstract: No abstract text available
Text: SN65LV1023A/SN65LV1224B 10ĆMHz TO 66ĆMHz, 10:1 LVDS SERIALIZER/DESERIALIZER SLLS621B − SEPTEMBER 2004 − REVISED JULY 2005 D 100-Mbps to 660-Mbps Serial LVDS Data D D D Payload Bandwidth at 10-MHz to 66-MHz System Clock Pin-Compatible Superset of NSM
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SN65LV1023A/SN65LV1224B
10MHz
66MHz,
SLLS621B
100-Mbps
660-Mbps
10-MHz
66-MHz
DS92LV1023/DS92LV1224
28-Pin
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SLLS526
Abstract: SN65LVDS1021DB SN65LVDS1212 SN65LVDS1212DB SN65LVDS1021
Text: SN65LVDS1021/SN65LVDS1212 10 MHz TO 40 MHz, 10:1 LVDS SERIALIZER/DESERIALIZER SLLS526 – FEBRUARY 2002 D D D 100–400 Mbps Serial LVDS Data Payload Bandwidth at 10 MHz to 40 MHz System Clock Pin-Compatible Superset of NSM DS92LV1021/DS92LV1212 Chipset Serializer/Deserializer Power
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SN65LVDS1021/SN65LVDS1212
SLLS526
DS92LV1021/DS92LV1212
28-Pin
SN65LVDS1021
SLLS526
SN65LVDS1021DB
SN65LVDS1212
SN65LVDS1212DB
SN65LVDS1021
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Untitled
Abstract: No abstract text available
Text: SN65LV1023A/SN65LV1224B 10ĆMHz TO 66ĆMHz, 10:1 LVDS SERIALIZER/DESERIALIZER SLLS621B − SEPTEMBER 2004 − REVISED JULY 2005 D 100-Mbps to 660-Mbps Serial LVDS Data D D D Payload Bandwidth at 10-MHz to 66-MHz System Clock Pin-Compatible Superset of NSM
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SN65LV1023A/SN65LV1224B
10MHz
66MHz,
SLLS621B
100-Mbps
660-Mbps
10-MHz
66-MHz
DS92LV1023/DS92LV1224
28-Pin
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100 p39
Abstract: FOOTPRINT TAJD 170/200MSPS outline of the heat slug for JEDEC AD9411 AD9430 TQFP-100 AD8351
Text: 10-Bit, 170/200 MSPS 3.3 V A/D Converter AD9411 FEATURES FUNCTIONAL BLOCK DIAGRAM SENSE VREF AGND DRGND DRVDD AVDD SCALABLE REFERENCE VIN+ VIN– CLK+ CLK– TRACK AND HOLD AD9411 ADC 10 10-BIT PIPELINE / CORE CLOCK MANAGEMENT LVDS OUTPUTS LVDS TIMING DATA,
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10-Bit,
AD9411
10-BIT
100-Lead
SV-100)
AD9411BSV-170
AD9411BSV-200
AD9411/PCB
SV-100
100 p39
FOOTPRINT TAJD
170/200MSPS
outline of the heat slug for JEDEC
AD9411
AD9430
TQFP-100
AD8351
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