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    LV165 Search Results

    LV165 Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    SN74LV165ADR Texas Instruments Parallel-Load 8-Bit Shift Registers 16-SOIC -40 to 125 Visit Texas Instruments Buy
    SN74LV165APWRE4 Texas Instruments Parallel-Load 8-Bit Shift Registers 16-TSSOP -40 to 125 Visit Texas Instruments Buy
    SN74LV165APWR Texas Instruments Parallel-Load 8-Bit Shift Registers 16-TSSOP -40 to 125 Visit Texas Instruments Buy
    SN74LV165ADRE4 Texas Instruments Parallel-Load 8-Bit Shift Registers 16-SOIC -40 to 125 Visit Texas Instruments Buy
    SN74LV165APWRG4 Texas Instruments Parallel-Load 8-Bit Shift Registers 16-TSSOP -40 to 125 Visit Texas Instruments Buy
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    LV165 Price and Stock

    Nexperia 74LV165D,118

    IC SHIFT REGISTER 8BIT 16SOIC
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    DigiKey 74LV165D,118 Cut Tape 83,584 1
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    74LV165D,118 Digi-Reel 83,584 1
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    Newark 74LV165D,118 Cut Tape 2,445 5
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    Rochester Electronics 74LV165D,118 41,420 1
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    TTI 74LV165D,118 Reel 5,000
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    TME 74LV165D,118 1,792 1
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    Avnet Asia 74LV165D,118 8 Weeks 7,500
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    Chip One Stop 74LV165D,118 Cut Tape 1,055
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    Texas Instruments SN74LV165ARGYR

    IC SHFT REG PARAL LD 8BIT 16VQFN
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    DigiKey SN74LV165ARGYR Digi-Reel 11,963 1
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    SN74LV165ARGYR Cut Tape 11,963 1
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    SN74LV165ARGYR Reel 11,666 3,000
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    Mouser Electronics SN74LV165ARGYR 87,463
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    Bristol Electronics SN74LV165ARGYR 116
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    Chip-Germany GmbH SN74LV165ARGYR 42,150
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    Win Source Electronics SN74LV165ARGYR 8,100
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    Texas Instruments SN74LV165ABQBR

    PARALLEL-LOAD EIGHT-BIT SHIFT RE
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    DigiKey SN74LV165ABQBR Cut Tape 8,890 1
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    Mouser Electronics SN74LV165ABQBR 2,570
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    Nexperia 74LV165APW,118

    IC 8BIT SHIFT REGISTER 16TSSOP
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    DigiKey 74LV165APW,118 Digi-Reel 6,726 1
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    74LV165APW,118 Cut Tape 6,726 1
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    74LV165APW,118 Reel 2,500
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    New Advantage Corporation 74LV165APW,118 10,000 1
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    Texas Instruments SN74LV165APWT

    IC REGISTR PAR-LOAD 8BIT 16TSSOP
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    DigiKey SN74LV165APWT Digi-Reel 4,714 1
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    SN74LV165APWT Reel 4,500 250
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    Win Source Electronics SN74LV165APWT 80,020
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    LV165 Datasheets Context Search

    Catalog Datasheet MFG & Type Document Tags PDF

    Untitled

    Abstract: No abstract text available
    Text: LV165A, LV165A PARALLEL-LOAD 8-BIT SHIFT REGISTERS SCLS402C – APRIL 1998 – REVISED MAY 2000 D D D D D EPIC  Enhanced-Performance Implanted CMOS Process 2-V to 5.5-V VCC Operation Support Mixed-Mode Voltage Operation on All Ports Latch-Up Performance Exceeds 250 mA Per


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    SN54LV165A, SN74LV165A SCLS402C LV165A CopyrighU001B, SDYU001N, SCET004, SCAU001A, SCEM132, PDF

    Untitled

    Abstract: No abstract text available
    Text: LV165A, LV165A PARALLEL-LOAD 8-BIT SHIFT REGISTERS SCLS402C – APRIL 1998 – REVISED MAY 2000 D D D D D EPIC  Enhanced-Performance Implanted CMOS Process 2-V to 5.5-V VCC Operation Support Mixed-Mode Voltage Operation on All Ports Latch-Up Performance Exceeds 250 mA Per


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    SN54LV165A, SN74LV165A SCLS402C LV165A SZZU001B, SDYU001M, SCAU001A, SN74LV165A, ////roarer/root/data13/imaging/BIT. PDF

    A115-A

    Abstract: C101 LV165A SN54LV165A SN74LV165A SN74LV165APWRG3
    Text: LV165A, LV165A PARALLEL-LOAD 8-BIT SHIFT REGISTERS SCLS402M − APRIL 1998 − REVISED DECEMBER 2010 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Support Mixed-Mode Voltage Operation on JESD 17 D ESD Protection Exceeds JESD 22 − 2000-V Human-Body Model A114-A


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    SN54LV165A, SN74LV165A SCLS402M 000-V A114-A) A115-A) SN54LV165A A115-A C101 LV165A SN54LV165A SN74LV165A SN74LV165APWRG3 PDF

    Untitled

    Abstract: No abstract text available
    Text: LV165A, LV165A PARALLEL-LOAD 8-BIT SHIFT REGISTERS SCLS402C – APRIL 1998 – REVISED MAY 2000 D D D D D EPIC  Enhanced-Performance Implanted CMOS Process 2-V to 5.5-V VCC Operation Support Mixed-Mode Voltage Operation on All Ports Latch-Up Performance Exceeds 250 mA Per


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    SN54LV165A, SN74LV165A SCLS402C LV165A SN74LV165AD SN74LV165ADBR SN74LV165ADGVR SN74LV165ADR SN74LV165APWR PDF

    LV165A

    Abstract: SN54LV165A SN74LV165A
    Text: LV165A, LV165A PARALLEL-LOAD 8-BIT SHIFT REGISTERS SCLS402C – APRIL 1998 – REVISED MAY 2000 D D D D D EPIC  Enhanced-Performance Implanted CMOS Process 2-V to 5.5-V VCC Operation Support Mixed-Mode Voltage Operation on All Ports Latch-Up Performance Exceeds 250 mA Per


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    SN54LV165A, SN74LV165A SCLS402C MIL-STD-883, SN54LV165A LV165A SN54LV165A SN74LV165A PDF

    Untitled

    Abstract: No abstract text available
    Text: LV165A, LV165A PARALLEL-LOAD 8-BIT SHIFT REGISTERS SCLS402L − APRIL 1998 − REVISED MAY 2010 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Support Mixed-Mode Voltage Operation on JESD 17 D ESD Protection Exceeds JESD 22 − 2000-V Human-Body Model A114-A


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    SN54LV165A, SN74LV165A SCLS402L 000-V A114-A) A115-A) SN54LV165A PDF

    lv165a

    Abstract: No abstract text available
    Text: LV165A, LV165A www.ti.com SCLS402N – APRIL 1998 – REVISED JULY 2013 PARALLEL-LOAD 8-BIT SHIFT REGISTERS Check for Samples: LV165A, LV165A FEATURES DESCRIPTION • • • The ’LV165A devices are parallel-load, 8-bit shift registers designed for 2-V to 5.5-V VCC operation.


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    SN54LV165A, SN74LV165A SCLS402N LV165A 000-V A114-A) A115-A) PDF

    A115-A

    Abstract: C101 SN74LV165A-EP SN74LV165AMPWREP
    Text: LV165A-EP PARALLEL-LOAD 8-BIT SHIFT REGISTER www.ti.com SCLS694 – JANUARY 2006 FEATURES • • • • • • • • • • 1 Controlled Baseline – One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of –55°C to 125°C


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    SN74LV165A-EP SCLS694 000-V A114-A) A115-A) A115-A C101 SN74LV165A-EP SN74LV165AMPWREP PDF

    Untitled

    Abstract: No abstract text available
    Text: LV165A, LV165A PARALLELĆLOAD 8ĆBIT SHIFT REGISTERS SCLS402K − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Support Mixed-Mode Voltage Operation on D All Ports Ioff Supports Partial-Power-Down Mode


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    SN54LV165A, SN74LV165A SCLS402K 000-V A114-A) A115-A) SN54LV165A PDF

    Untitled

    Abstract: No abstract text available
    Text: LV165A, LV165A PARALLELĆLOAD 8ĆBIT SHIFT REGISTERS SCLS402K − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Support Mixed-Mode Voltage Operation on D All Ports Ioff Supports Partial-Power-Down Mode


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    SN54LV165A, SN74LV165A SCLS402K 000-V A114-A) A115-A) SN54LV165A PDF

    Untitled

    Abstract: No abstract text available
    Text: LV165A, LV165A PARALLEL-LOAD 8-BIT SHIFT REGISTERS SCLS402M − APRIL 1998 − REVISED DECEMBER 2010 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Support Mixed-Mode Voltage Operation on JESD 17 D ESD Protection Exceeds JESD 22 − 2000-V Human-Body Model A114-A


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    SN54LV165A, SN74LV165A SCLS402M 000-V A114-A) A115-A) SN54LV165A PDF

    7054F

    Abstract: BC564A HA13563 AC123A HITACHI microcontroller H8 534 manual IC 74LS47 AC538 BC245A 2SK3235 HA13557
    Text: INDEX General General Information Semiconductor Packages Sales Locations Microcontroller Microcontroller General MultiChipModules Smart Card Micro. Overview Micro. Shortform Micro. Hardware Manual Micro. Program. Manual Micro. Application Notes LCD Controller / Driver


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    2sc4537 2sc454. 2sc4591 2sc4592 2sc4593 2sc460. 2sc4628 2sc4629 2sc4643 2sc4680 7054F BC564A HA13563 AC123A HITACHI microcontroller H8 534 manual IC 74LS47 AC538 BC245A 2SK3235 HA13557 PDF

    SN54LV165

    Abstract: SN74LV165 SN74LV165D SN74LV165DBLE SN74LV165DR SN74LV165PWLE
    Text: LV165, LV165 PARALLEL-LOAD 8-BIT SHIFT REGISTERS SCES007B – MARCH 1995 – REVISED APRIL 1996 D D D D D EPIC Enhanced-Performance Implanted CMOS 2-µ Process Typical VOLP (Output Ground Bounce) < 0.8 V at VCC, TA = 25°C Typical VOHV (Output VOH Undershoot)


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    SN54LV165, SN74LV165 SCES007B MIL-STD-883C, JESD-17 300-mil SN54LV165 SN54LV165 SN74LV165 SN74LV165D SN74LV165DBLE SN74LV165DR SN74LV165PWLE PDF

    SN74 schmitt trigger

    Abstract: SDYU001 SN54LV00A SN54LV02A SN54LV04A SN54LV05A SN54LV08A SN54LV14A SN54LV32A SN54LV74A
    Text: LVC and LV LowĆVoltage CMOS Logic Data Book 1998 Logic Products General Information LVC Gates and MSI LVC Octals LVC Widebus LVC 3.3-V to 5-V Translators and Cable Drivers LV Gates and MSI LV Octals Application Reports Mechanical Data LVC and LV Low-Voltage CMOS Logic


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    MIL-STD-1835 GDFP2-F20 SN74 schmitt trigger SDYU001 SN54LV00A SN54LV02A SN54LV04A SN54LV05A SN54LV08A SN54LV14A SN54LV32A SN54LV74A PDF

    Untitled

    Abstract: No abstract text available
    Text: LV165A-EP PARALLEL-LOAD 8-BIT SHIFT REGISTER www.ti.com SCLS694 – JANUARY 2006 FEATURES • • • • • • • • • • 1 Controlled Baseline – One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of –55°C to 125°C


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    SN74LV165A-EP SCLS694 PDF

    Untitled

    Abstract: No abstract text available
    Text: LV165A, LV165A PARALLELĆLOAD 8ĆBIT SHIFT REGISTERS SCLS402K − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Support Mixed-Mode Voltage Operation on D All Ports Ioff Supports Partial-Power-Down Mode


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    SN54LV165A, SN74LV165A SCLS402K 000-V A114-A) A115-A) SN54LV165A PDF

    Untitled

    Abstract: No abstract text available
    Text: LV165A-EP PARALLEL-LOAD 8-BIT SHIFT REGISTER www.ti.com SCLS694 – JANUARY 2006 FEATURES • • • • • • • • • • 1 Controlled Baseline – One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of –55°C to 125°C


    Original
    SN74LV165A-EP SCLS694 PDF

    Untitled

    Abstract: No abstract text available
    Text: LV165A, LV165A PARALLEL-LOAD 8-BIT SHIFT REGISTERS SCLS402K − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Support Mixed-Mode Voltage Operation on D All Ports Ioff Supports Partial-Power-Down Mode Operation


    Original
    SN54LV165A, SN74LV165A SCLS402K 000-V A114-A) A115-A) SN54LV165A PDF

    Untitled

    Abstract: No abstract text available
    Text: LV165A, LV165A PARALLEL-LOAD 8-BIT SHIFT REGISTERS SCLS402M − APRIL 1998 − REVISED DECEMBER 2010 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Support Mixed-Mode Voltage Operation on JESD 17 D ESD Protection Exceeds JESD 22 − 2000-V Human-Body Model A114-A


    Original
    SN54LV165A, SN74LV165A SCLS402M 000-V A114-A) A115-A) SN54LV165A PDF

    Untitled

    Abstract: No abstract text available
    Text: LV165A, LV165A PARALLEL-LOAD 8-BIT SHIFT REGISTERS SCLS402H – APRIL 1998 – REVISED JANUARY 2003 LV165A . . . J OR W PACKAGE LV165A . . . D, DB, DGV, NS, OR PW PACKAGE TOP VIEW 3 14 4 13 5 12 6 11 7 10 8 9 VCC CLK INH D C B A SER QH CLK


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    SN54LV165A, SN74LV165A SCLS402H 000-V A114-A) A115-A) SN54LV165A PDF

    74HC165

    Abstract: Toshiba hay 22 forsythe 16V8 74ALVC16244 74HC595 GAL16LV8D QS3257 QS3384 MOTHERBOARD ibm rev.1.5
    Text: Pyxis Chipset Spec December 5, 1996 Rev X2.1 Authors: Reinhard Schumann , Schumann@eng.pko.dec.com Don Rice, Rice@eng.pko.dec.com Digital Equipment Corporation 1995, All Rights Reserved The specifications contained herein are confidential and proprietary. The information in this document is


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    21-Aug-1996 5-Dec-1996 74HC165 Toshiba hay 22 forsythe 16V8 74ALVC16244 74HC595 GAL16LV8D QS3257 QS3384 MOTHERBOARD ibm rev.1.5 PDF

    Untitled

    Abstract: No abstract text available
    Text: LV165, LV165 PARALLEL-LOAD 8-BIT SHIFT REGISTERS SCES007B – MARCH 1995 – REVISED APRIL 1996 D D D D D EPIC Enhanced-Performance Implanted CMOS 2-µ Process Typical VOLP (Output Ground Bounce) < 0.8 V at VCC, TA = 25°C Typical VOHV (Output VOH Undershoot)


    Original
    SN54LV165, SN74LV165 SCES007B MIL-STD-883C, JESD-17 300-mil SN54LV165 PDF

    LV138

    Abstract: LV245 LV273 Flip-Flops lv373 LV164 LV125 LV174
    Text: Contents Page LV Gates/MSI/Octals ’LVOO ’LV02 ’LV04 ’LVU04 ’LV08 ’LV14 ’LV32 ’LV74 'LV125 LV138 LV164 'LV165LV174 'LV240 'LV244 LV245 'LV273 'LV373 LV374 LV573 'LV574 6-2 Quadruple 2-Input Positive-NAND G a t e s . 6-3


    OCR Scan
    LVU04 LV125 LV138 LV164 LV165 LV174 LV240 LV244 LV245 LV273 LV138 LV245 LV273 Flip-Flops lv373 LV164 LV125 LV174 PDF

    25x16v

    Abstract: No abstract text available
    Text: LV165, LV165 PARALLEL-LOAD 8-BIT SHIFT REGISTERS SCES007B - MARCH 1996 - REVISED APRIL 1996 EPIC Enhanced-Performance Implanted CMOS 2-n Process typical Vq l p (Output Ground Bounce) < 0.8 V at V c c . Ta = 25°C Typical V q h v (Output V q h Undershoot)


    OCR Scan
    SN54LV165, SN74LV165 SCES007B SN54LV165. SN74LV165 MIL-STD-883C, JESD-17 25x16v PDF