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    LSI COREWARE LIBRARY Search Results

    LSI COREWARE LIBRARY Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    DRV2625YFFR Texas Instruments Advanced ERM & LRA Haptics Driver with Smart Loop and Embedded Effects Library 9-DSBGA -40 to 85 Visit Texas Instruments Buy
    DRV2625YFFT Texas Instruments Advanced ERM & LRA Haptics Driver with Smart Loop and Embedded Effects Library 9-DSBGA -40 to 85 Visit Texas Instruments Buy
    DRV2605YZFT Texas Instruments Haptic Driver for ERM/LRA with Built-In Library and Smart Loop Architecture 9-DSBGA -40 to 85 Visit Texas Instruments Buy
    DRV2605YZFR Texas Instruments Haptic Driver for ERM/LRA with Built-In Library and Smart Loop Architecture 9-DSBGA -40 to 85 Visit Texas Instruments Buy
    DRV2605LDGSR Texas Instruments Haptic Driver for ERM and LRA with Built-In Library and Smart Loop Architecture 10-VSSOP -40 to 85 Visit Texas Instruments Buy

    LSI COREWARE LIBRARY Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    Untitled

    Abstract: No abstract text available
    Text: CW001007 ARM7TDMI Microprocessor Core Datasheet The LSI Logic CW001007 core is an implementation of the Advanced RISC Machines ARM7TDMI 32-bit RISC microprocessor developed by Advanced RISC Machines. The CW1007 meets the requirements of the LSI Logic CoreWare methodology and is implemented using LSI Logic


    Original     		PDF CW001007 32-bit CW1007 25-micron G11-p G11-v

    MR4010

    Abstract: STR MR4010 SW-SPDT-mom MR4010 circuit HC 5287 LDP16 J132 regulator BDMR4010 2 pin dip switch str 2105
    Text: MiniRISC BDMR4010 Evaluation Board User’s Guide A CoreWare Product Preliminary Order Number C14035 This document is preliminary. As such, it contains data derived from functional simulations and performance estimates. LSI Logic has not verified either the


    Original     		PDF BDMR4010 C14035 DB15-000043-00, MR4010 STR MR4010 SW-SPDT-mom MR4010 circuit HC 5287 LDP16 J132 regulator BDMR4010 2 pin dip switch str 2105

    TAG 8822

    Abstract: tag 9327 maa 502 CWDSP1650 0x0000-0xFDFF C15018 LSI coreware library
    Text: CWDSP1650 OakDSPCore Preliminary Datasheet Description The CWDSP1650 OakDSPCore, a component of the LSI Logic CoreWare Library, is a 16-bit, high-performance, fixed-point Digital Signal Processing DSP core for midrange to high-end telecommunications and consumer electronics applications. The core provides a


    Original     		PDF CWDSP1650 CWDSP1650 16-bit, TAG 8822 tag 9327 maa 502 0x0000-0xFDFF C15018 LSI coreware library

    ccu g11

    Abstract: CWDSP1650 CWDSP1670 "vector instructions" saturation arithmetic left shift
    Text: CWDSP1670 DSP Core Preliminary Datasheet The CWDSP1670 DSP Core, a component of the LSI Logic CoreWare Library, is a 16-bit, high-performance, fixed-point Digital Signal Processing DSP core for mid- to high-end telecommunications and consumer electronics applications. It is a low-cost, high-performance


    Original     		PDF CWDSP1670 CWDSP1670 16-bit, G11TM-p G11-v CWDSP1671) CWDSP1670, ccu g11 CWDSP1650 "vector instructions" saturation arithmetic left shift

    LR33300

    Abstract: yx 801 cw33300 LSI CoreWare CW33300 Enhanced Self-Embedding Processor Core tag 8638 Rato* RT 1072 DI-22 DI-31 LR3330
    Text: MiniRISC CW4011 Superscalar Microprocessor Core Technical Manual A CoreWare® Product ® Order Number C14040.A Document DB14-000064-01, Second Edition May 1999 This document describes revision A of LSI Logic Corporation’s MiniRISC® CW4011 Superscalar Microprocessor Core and will remain the official reference


    Original     		PDF CW4011 C14040 DB14-000064-01, CW4011 LR33300 yx 801 cw33300 LSI CoreWare CW33300 Enhanced Self-Embedding Processor Core tag 8638 Rato* RT 1072 DI-22 DI-31 LR3330

    LSI 1394a

    Abstract: pht 094 IEC61883 LSI Logic ASIC
    Text: 1394 Node Controller Core IEEE 1394a Node Controller Core Features Overview The 1394 Node Controller Core is a member of the LSI Logic CoreWare family of design building blocks. The 1394 Node Controller Core macro, when combined with a CPU processor and PHY core, provides a fully functional integrated


    Original     		PDF 1394a 1394a-2000 LSI 1394a pht 094 IEC61883 LSI Logic ASIC

    LSI 1394a

    Abstract: LSI LOGIC pht 094 IEC61883
    Text: 1394 Node Controller Core IEEE 1394a Node Controller Core Features Overview The 1394 Node Controller Core is a member of the LSI Logic CoreWare family of design building blocks. The 1394 Node Controller Core macro, when combined with a CPU processor and PHY core, provides a fully functional integrated


    Original     		PDF 1394a 1394a-2000 LSI 1394a LSI LOGIC pht 094 IEC61883

    modified harvard architecture

    Abstract: 3955K oak dsp CWDSP1640
    Text: CWDSP1640 Oak DSP Core Datasheet Description The CWDSP1640 Oak DSP Core, a component of the LSI Logic CoreWare Library, is a 16-bit, high-performance, fixed-point Digital Signal Processing DSP core designed for middle to high-end telecommunications applications and consumer electronics. The core provides a low-cost, high-performance solution for applications that require low power and


    Original     		PDF CWDSP1640 CWDSP1640 16-bit, modified harvard architecture 3955K oak dsp

    pal 007c

    Abstract: b1100 nec LDP16 sulzer s7 7-segment countdown timer MDP36 100LQ128 3pin round shell connector DP83932B LT1084CT-3.3
    Text: MiniRISC BDMR4011 Evaluation Board User’s Guide A CoreWare® Product March 1998 ® Order Number XXXXX Document DB15-000055-00, First Edition March 1998 This document describes revision A of LSI Logic Corporation’s BDMR4011 Evaluation Board and will remain the official reference source for all revisions/releases of this product until rescinded by an update.


    Original     		PDF BDMR4011 DB15-000055-00, respons3580 pal 007c b1100 nec LDP16 sulzer s7 7-segment countdown timer MDP36 100LQ128 3pin round shell connector DP83932B LT1084CT-3.3

    EZ4021

    Abstract: No abstract text available
    Text: EZ4021 MiniRISC EasyMACRO TM Integrated MiniRISC ® MIPS Microprocessor Core Overview The EZ4021 extends the LSI Logic MIPS MiniRISC® family with a high performance 64-bit microprocessor. The EZ4021 EasyMACRO is an optimized implementation of a synthesizeable core that operates up to 250MHz under worst


    Original     		PDF EZ4021 64-bit 250MHz 64-bit

    verilog code for 16 bit risc processor

    Abstract: MIPS16 mips vhdl code 4102TM verilog code for 32 bit risc processor vhdl code mips code vhdl code for uart vhdl code for risc processor 32 bit risc processor using vhdl BDMR4102
    Text: TinyRISC 4102 MIPS Processor Core Overview The 4102TM TinyRISC MIPS processor core extends LSI Logic’s embedded RISC processor family. This core is the second generation of the widely used TinyRISCTM MIPS processor implementation using the MIPS16, Application


    Original     		PDF 4102TM MIPS16, 16-bit 32-bit MIPS16 MIPS16 85MHz TR4102 C20027 verilog code for 16 bit risc processor mips vhdl code verilog code for 32 bit risc processor vhdl code mips code vhdl code for uart vhdl code for risc processor 32 bit risc processor using vhdl BDMR4102

    LSI coreware library

    Abstract: LSI LOGIC OakDSPCore "Hot Plug and Play"
    Text: USB Host Core Host Core for Universal Serial Bus Solutions Overview The USB Host Core, a component of LSI Logic’s comprehensive USB solution set, is a flexible and configurable core that manages and generates the Universal Serial Bus, providing support of USB peripherals in highly integrated embedded systems.


    Original     		PDF

    ARM926EJ-S

    Abstract: ARM processor data flow ARM926EJScore embedded trace macrocell ARM926EJ etm lsi logic
    Text: 266/200MHz ARM926EJ-S Cores with Linux and Java Support OVERVIEW FEATURES LSI Logic offers the ARM926EJ-S processor core synthesized onto both our Gflx 0.11 micron drawn and G12P 0.18 micron (drawn) high performance process technologies. • 266MHz Gflx ARM926EJ-S


    Original     		PDF 266/200MHz ARM926EJ-STM ARM926EJ-S 266MHz ARM926EJ-S ARM processor data flow ARM926EJScore embedded trace macrocell ARM926EJ etm lsi logic

    LSI LOGIC

    Abstract: "USB Transceiver" LSI coreware library "Hot Plug and Play"
    Text: USB Function Core Overview LSI Logic’s USB Function Core is a flexible and configurable core interfacing a peripheral function to the Universal Serial Bus and enabling the design of highly integrated peripheral single-chip systems. Combining the USB Function core and LSI Logic’s USB transceiver I/Os with


    Original     		PDF C20022 LSI LOGIC "USB Transceiver" LSI coreware library "Hot Plug and Play"

    ARM1156T2-S

    Abstract: AMBA AXI to APB BUS Bridge AMBA AXI to APB BUS Bridge architecture PL022 AXI-64 interface ARM processor data flow PL300 AMBA AHB to AXI AMBA AHB bus protocol ARM1156T2S
    Text: ARM1156T2-S TCM-only Processor with ECC Protection and Reference Design CW001145 FEATURES • 450 MHz timing-closed hardmac OVERVIEW The LSI Logic implementation of the ARM1156T2-S processor for cell-based ASIC provides an integration friendly solution for applications like mass storage


    Original     		PDF ARM1156T2-S CW001145 ARM966E-S C20069 AMBA AXI to APB BUS Bridge AMBA AXI to APB BUS Bridge architecture PL022 AXI-64 interface ARM processor data flow PL300 AMBA AHB to AXI AMBA AHB bus protocol ARM1156T2S

    G12-l

    Abstract: LSI Logic ASIC g12 High Voltage G12L g12 transistor G12 000
    Text: G12 ASIC Cell-Based Product Features/ Benefits Twelfth Generation ASIC Technology • ASIC technology with 0.18 micron L-drawn Overview LSI Logic’s G12 ASIC Cell-Based product, with its three digital libraries, offers unprecedented options for system ASIC designers to optimize their ASIC or


    Original     		PDF 18-micron 13-micron B20023 G12-l LSI Logic ASIC g12 High Voltage G12L g12 transistor G12 000

    LSI Logic ASIC

    Abstract: USB Hub LSI coreware library USB PANEL LSI LOGIC
    Text: USB Hub Core Hub Core for Universal Serial Bus Solutions Overview LSI Logic's USB Hub Core, a component of LSI Logic’s comprehensive Universal Serial Bus USB solution set, is a flexible and configurable core that supports additional USB connections within a USB system, enabling the


    Original     		PDF

    011U

    Abstract: LSI coreware library ARM11 lsi logic ARM11 "instruction set summary" armv5te cp14 ARM coprocessor
    Text: DATASHEET 0.11µ ARM966E-S Processor cw001163_1_0 October 2004 Preliminary DB08-000257-00 This document is preliminary. As such, it contains data derived from functional simulations and performance estimates. LSI Logic has not verified either the functional descriptions, or the electrical and mechanical specifications using


    Original     		PDF ARM966E-STM cw001163 DB08-000257-00 DB08-000257-00, ARM966E-S 011U LSI coreware library ARM11 lsi logic ARM11 "instruction set summary" armv5te cp14 ARM coprocessor

    ARMv5TE instruction set

    Abstract: ARM946E-STM ARMv5TE ARM946E-S ARM processor data flow design flow soc architecture ARM966E-S CW001100 TCMS
    Text: CW001100 - 200 MHz Synthesized ARM946E-S Core with Cache Memories OVERVIEW FEATURES AND BENEFITS The CW001100 processor core is a 200 MHz implementation of the popular ARM946E-S™, synthesized onto LSI Logic’s G12P 0.18 micron high performance process technology.


    Original     		PDF CW001100 ARM946E-STM ARM946E-STM, ARM946E-S, R20050 ARMv5TE instruction set ARMv5TE ARM946E-S ARM processor data flow design flow soc architecture ARM966E-S TCMS

    design flow soc architecture

    Abstract: ARM processor data flow ARM9E-S ARM9E-STM ARM966E-S CW001105 ARMv5TE instruction set ARMv5TE LSI cell library
    Text: CW001105 - 200 MHz Synthesized ARM966E-S Core OVERVIEW FEATURES AND BENEFITS The CW001105 processor core is a 200 MHz implementation of the popular ARM966E-S™, synthesized onto LSI Logic’s G12P 0.18 micron high performance process technology. • 200 MHz Operating frequency


    Original     		PDF CW001105 ARM966E-S ARM966E-STM, ARM966E-S, C20042 design flow soc architecture ARM processor data flow ARM9E-S ARM9E-STM ARMv5TE instruction set ARMv5TE LSI cell library

    PQ-32/AMS-DTL-23053/4 ATUM

    Abstract: pid u 13t lsi r3000 LSI coreware library CW4001
    Text: LSI LOGIC Description MiniRISC MR4001 Microprocessor Lead Vehicle Preliminary Datasheet The MiniRISC MR4001 Microprocessor Lead Vehicle is a chip implementation of the MiniRISC CW4001 Microprocessor, a component of LSI Logic’s CoreWare Library. The


    OCR Scan     		PDF MR4001 CW4001 32-bit R4000 PQ-32/AMS-DTL-23053/4 ATUM pid u 13t lsi r3000 LSI coreware library

    coreware graphics

    Abstract: verilog code for superscalar mips
    Text: LSI LOGIC Description MiniRISC CW4010 Superscalar Microprocessor Core Preliminary D atash eet LSI Logic Corporation has developed the MiniRISC CW4010 Superscalar Microprocessor Core, the world’s first MIPS-ll-compatible superscalar core, using LSI Logic’s CoreWare


    OCR Scan     		PDF CW4010 80-MHz coreware graphics verilog code for superscalar mips

    CW4001

    Abstract: No abstract text available
    Text: LSI LOGIC CWDSP1650 OakDSPCore Prelim inary Datasheet Description The CW DSP1650 OakDSPCore, a component of the LSI Logic CoreWare Library, is a 16-bit, high-performance, fixed-point Digital Signal Processing DSP) core for midrange to high-end telecommunications and consumer electronics applications. The core provides a


    OCR Scan     		PDF CWDSP1650 DSP1650 16-bit, MCLK/16 MCLK/16384 CW4001

    oak dsp

    Abstract: "vector instructions" saturation
    Text: LSI LOGIC Description CWDSP1640 Oak DSP Core Datasheet The CWDSP1640 Oak DSP Core, a component of the LSI Logic CoreWare Library, is a 16-bit, high-performance, fixed-point Digital Signal Processing DSP core designed for mid­ dle to high-end telecommunications applications and consumer electronics. The core pro­


    OCR Scan     		PDF CWDSP1640 16-bit, oak dsp "vector instructions" saturation