by118
Abstract: No abstract text available
Text: CY8C23433, CY8C23533 PSoC Mixed-Signal Aray Features • ■ Powerful Harvard Architecture Processor ❐ M8C processor speeds to 24 MHz ❐ 8x8 multiply, 32-bit accumulate ❐ Low power at high speed ❐ 3.0 to 5.25V operating voltage ❐ Industrial temperature range: -40°C to +85°C
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CY8C23433,
CY8C23533
32-bit
14-bit
by118
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MO-248
Abstract: CY8C21434-24LTXI CY8C21234 CY8C21334 CY8C21434 CY8C21534 CY8C21634 CY8C29X
Text: CY8C21634, CY8C21534 CY8C21434, CY8C21334, CY8C21234 PSoC Mixed-Signal Array Features • ■ Powerful Harvard Architecture Processor ❐ M8C Processor Speeds to 24 MHz ❐ Low power at high speed ❐ 2.4V to 5.25V Operating Voltage ❐ Operating Voltages Down to 1.0V using On-Chip Switch
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CY8C21634,
CY8C21534
CY8C21434,
CY8C21334,
CY8C21234
MO-248
CY8C21434-24LTXI
CY8C21234
CY8C21334
CY8C21434
CY8C21534
CY8C21634
CY8C29X
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MDK150
Abstract: md1p LR3000
Text: Chapter 5 LR32D04 DRAM Data Buffer This chapter describes the LR32D04 DRAM Data Buffers. Chapter 5 is organized into these sections: • General Description ■ Signal Definitions ■ Data Buffer Configurations ■ Specifications Because the operation of the LR32D04 is closely tied to the LR3203
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LR32D04
LR3203
LR3203,
LR32D
MDK150
md1p
LR3000
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LD11
Abstract: LD12 LR3203 LR3205 LR32D04 LR3000
Text: Chapter 5 LR32D04 DRAM Data Buffer This chapter describes the LR32D04 DRAM Data Buffers. Chapter 5 is organized into these sections: • General Description ■ Signal Definitions ■ Data Buffer Configurations ■ Specifications Because the operation of the LR32D04 is closely tied to the LR3203
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LR32D04
LR3203
LR3203,
LD11
LD12
LR3205
LR3000
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k535
Abstract: CDB22 LR3000 cxl tuner diagram interfacing of memory devices with 8086 LB1K LR3202A LR3203 LR3205 LR32D04
Text: Chapter 3 LR3202A L-Bus Controller This chapter describes the LR3202A L-Bus Controller. Chapter 3 is organized into these sections: • General Description ■ Configuring the LR3202A ■ Programming the System Control Registers ■ Signal Definitions ■ L-Bus Operation
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LR3202A
LR3202A
k535
CDB22
LR3000
cxl tuner diagram
interfacing of memory devices with 8086
LB1K
LR3203
LR3205
LR32D04
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53c90 NCR
Abstract: LR3205 LR3000 LR3000A 53c90
Text: Chapter 6 LR3205 Block Transfer Buffer This chapter describes the LR3205 Block Transfer Buffer. Chapter 6 is organized into these sections: 6.1 General Description a General Description • Concepts ■ Programming the Internal Registers ■ Signal Definitions
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LR3205
LR3000
LR3202A
53c90 NCR
LR3000A
53c90
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LR3000
Abstract: LR3000A
Text: Chapter 3 LR3202A L-Bus Controller This chapter describes the LR3202A L-Bus Controller. Chapter 3 is organized into these sections: • General Description ■ Configuring the LR3202A ■ Programming the System Control Registers ■ Signal Definitions ■ L-Bus Operation
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LR3202A
LR3202A
LR3000
LR3000A
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C1A13
Abstract: LR3000 DRAM controller dram memory 256kx4 lad2 5v LB03 LR3202A LR3203 LR3205 LR32D04
Text: Chapter 4 LR3203 DRAM Controller This chapter describes the LR3203 DRAM Controller. Chapter 4 is orga nized into these sections: • General Description ■ Concepts ■ Configuring the LR3203 ■ Signal Definitions ■ L-Bus Interface ■ DRAM Configurations
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LR3203
LR3203
LR32D04
C1A13
LR3000
DRAM controller
dram memory 256kx4
lad2 5v
LB03
LR3202A
LR3205
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LR3000
Abstract: 8196 LR3000 User Manual lr2000 LR3201 mps 0709 LR3000A RST01 mps 1410
Text: Chapter 2 LR3201 Reset/Interrupt Controller This chapter describes the LR3201 Reset/Interrupt Controller. This chapter is organized into these sections: • General Description ■ Reset Operation ■ Interrupt Operation ■ Signal Definitions ■ Interfacing to the LR3201
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LR3201
LR3201
LR3201.
LR3000
8196
LR3000 User Manual
lr2000
mps 0709
LR3000A
RST01
mps 1410
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53c90 NCR
Abstract: bdp 620 LR3000 53c90 concept igt 001 0C00 LR3202A LR3205
Text: Chapter 6 LR3205 Block Transfer Buffer This chapter describes the LR3205 Block Transfer Buffer. Chapter 6 is organized into these sections: • General Description ■ Concepts ■ Programming the Internal Registers ■ Signal Definitions ■ B-Bus Interface
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LR3205
LR3000
LR3202A
53c90 NCR
bdp 620
53c90
concept igt 001
0C00
LR3202A
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IR3203
Abstract: LR3000
Text: Chapter 4 LR3203 DRAM Controller This chapter describes the LR3203 DRAM Controller. Chapter 4 is orga nized into these sections: • General Description ■ Concepts ■ Configuring the LR3203 ■ Signal Definitions ■ L-Bus Interface ■ DRAM Configurations
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LR3203
LR32D04
IR3203
LR3000
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