21CFR1040
Abstract: 21CFR1040.10 10g DFB Duplex LC InGaAs ES105 ES1052-LPTTA
Text: Single-Mode LC XFP Transceiver For 10Gigabit Ethernet & 10G Fibre Channel ES1052-LPTTA Preliminary Data Sheet Features • • • • • • • • • • • • • 1310nm DFB laser Class 1 Laser Safety Conformance Links up to 10km Compliant with specifications for IEEE-802.3ae
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10Gigabit
ES1052-LPTTA
1310nm
IEEE-802
10GBASE-L)
51875Gbps
10Gbps
21CFR1040
21CFR1040.10
10g DFB
Duplex LC InGaAs
ES105
ES1052-LPTTA
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93L18
Abstract: ScansUX992
Text: LPTTL/MSI 93L18 LOW POWER EIGHT-INPUT PRIORITY ENCODER D E S C R IP T IO N — The L P T T L /M S I 9 3 L 1 8 is a Multipurpose Encoder designed to accept eight inputs and produce a binary weighted code of the highest order input. The circuit uses T T L technology for
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93L18
ScansUX992
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93L21
Abstract: truth table for 1 to 4 decoder ScansUX992
Text: LPTTL/MSI 93L21 LOW POWER DUAL ONE-OF-FOUR DECODER DESCRIPTIO N — The LPTTL/M SI 93L21 consists of two independent multipurpose decoders, each designed to accept two inputs and provide four mutually exclusive outputs. In addition an active LOW enable input is provided for each decoder which gives demultiplexing capability. The circuit uses T TL
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93L21
16-LEAD
truth table for 1 to 4 decoder
ScansUX992
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93L11
Abstract: hd12d ScansUX992
Text: LPTTL/MSI 93L11 LOW POWER ONE-OF-SIXTEEN DECODER DESCRIPTIO N — The LP T TL/M S I 93L11 is a Multi-Purpose Decoder designed to accept fo u r inputs and provide 16 m utually exclusive outputs. The circu it uses T T L technology and is com patible w ith the
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93L11
24-LEAD
hd12d
ScansUX992
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93L14
Abstract: ScansUX992
Text: LPTTL/MSI 93L14 LOW POWER QUAD LATCH D ESC R IP TIO N — The LPTTL/M SI 93L14 is a multifunctional 4-Bit Latch. The latch is designed for general purpose storage applications in high speed digital systems. The 93L14 uses T T L technology and is compatible with the Fairchild T T L family. All inputs feature diode clamping to reduce negative
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93L14
16-LEAD
ScansUX992
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93L12
Abstract: ScansUX992
Text: LPTTL/MSI 93L12 LOW POWER EIGHT-INPUT MULTIPLEXER D E S C R IP T IO N — The L P T T L /M S I 9 3 L 1 2 is a m onolithic, medium speed, eight input digital M u lti plexer. It provides in one package the ab ility to select one bit of data from up to eight sources. The
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93L12
ScansUX992
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circuit of 8-1 multiplexer
Abstract: circuit diagram of 8-1 multiplexer 93L09 Fairchild 93l09 two 81 multiplexer Truth table of 16 to 1 multiplexer ScansUX992
Text: LPTTL/MSI 93L09 LOW POWER DUAL FOUR-INPUT MULTIPLEXER D E S C R IP T IO N — The LPT TL/M SI 93L09 is a Monolithic, Medium Speed, Dual 4-Input Digital Multiplexer. It consists of two multiplexing circuits with common input select logic. Each circuit contains four inputs and fully buffered complementary outputs. In addition to operating as a multi
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93L09
circuit of 8-1 multiplexer
circuit diagram of 8-1 multiplexer
Fairchild 93l09
two 81 multiplexer
Truth table of 16 to 1 multiplexer
ScansUX992
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9L04
Abstract: No abstract text available
Text: LPTTL/SSI 9L04 LOW POWER HEX INVERTER This M a te r i a l C o p y r i g h t e d By Its R e s p e c t i v e M a n u f a c t u r e r F A IR C H IL D LPTTL/SS I 9 L0 4 A B S O L U T E M A X I M U M R A T IN G S above w h ic h th e u se fu l lif e m a y be .mpaire<JJ
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14-LE
9L04
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93L22
Abstract: ScansUX992 fairchild 93L22
Text: LPTTL/MSI 93L22 LOW POWER QUAD TW O-INPUT MULTIPLEXER D E S C R IP T IO N — The L P T T L /M S I 9 3 L 2 2 is a m onolithic, medium speed. Quad T w o -In p u t Digital M u ltip lexe r, constructed w ith the Fairchild Planar* epitaxial process. It consists of fo ur m ultiplexing
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93L22
16-LEAD
ScansUX992
fairchild 93L22
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93L00
Abstract: ScansUX991
Text: LPTTL/MSI 9 3 LOO LOW POWER 4-BIT SHIFT REGISTER D E S C R IP T IO N — T h e L P T T L /M S I 9 3 L 0 0 4 -B it S h ift R egister is a m e d iu m speed m u lti-fu n c tio n a l sequential lo g ic b lo c k , useful in a w id e v a rie ty o f register and c o u n te r a p p lic a tio n s . As a register it m ay
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93LOO
93L00
16-LEAD
ScansUX991
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LITRONIX
Abstract: LITRONIX Phototransistors LPT110A tachometer LPT100 LPT100A LPT100B LPT110 LPT110B
Text: Litronix Semiconductors Phototransistors D IM E N S IO N S LPT100 Series Phototransistor LPT 1 0 0 /L P T IQOA/LPTtOOB D E S C R IP T IO N Th e LPT100 series is a highly stable phototransistor in a ceramic case. They are Intended for use in position detectors, burglar alarms, optical
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LPT100
100mW
Cto85Â
LPT110/lPT110A/LPTH0B
34607R
LITRONIX
LITRONIX Phototransistors
LPT110A
tachometer
LPT100A
LPT100B
LPT110
LPT110B
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Fairchild dtl catalog
Abstract: dtl catalog fairchild 93L10 93L16 93L10-93L16 ScansUX992
Text: LPTTL/MSI 93L10-93L16 LOW POWER BCD DECADE C0UNTER/4-BIT BINARY COUNTER DESCR IPTIO N — The 9 3 L 1 0 is a High Speed Synchronous BCD Decade Counter and the 9 3 L 1 6 is a High Speed Synchronous 4-Bit Binary Counter. They are synchronously presetable, multifunctional
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93L10-93L16
93L10
93L16
Fairchild dtl catalog
dtl catalog fairchild
ScansUX992
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93L24
Abstract: F 93L24 ScansUX992
Text: LPTTL/MSI 93L24 LOW POWER 5-BIT COMPARATOR D E S C R IP T IO N — Th e L P T T L /M S I 9 3 L 2 4 is a M e d iu m Speed E xpandable C o m p a ra to r w h ic h provides co m p a riso n betw een tw o 5 -b it w ord s and gives three o u tp u ts , "less th a n ", "g re a te r th a n ” , and "e q u a l
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93L24
16-LEAD
F 93L24
ScansUX992
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9L24
Abstract: ScansUX997
Text: LPTTL/SSI 9L24 LOW POWER DUAL JK OR D FLIP-FLOP DESCRIPTIO N — The Low Power TTL/SSI 9L24 consists of two completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D flip-flop by simply connecting the J and K pins
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16-LEAD
500ns-
9L24
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9L00
Abstract: zi11 ScansUX997
Text: LPTTL/SSI 9L00 LOW POWER QUAD 2-INPUT NAND GATE DESCRIPTION — The low power TTL/SSI 9L00 consists of fo u r N A N D gates. Each gate has tw o inputs and perform s positive logic. The 9L00 is designed fo r low power and medium speed operation. LOGIC SYM BO L
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14-LEAD
600fi
9L00
zi11
ScansUX997
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93L08
Abstract: ScansUX992
Text: LPTTL/MSI 93L08 LOW POWER DUAL FOUR-BIT LATCH DESCRIPTIO N The LPTTL/M SI 9 3 L 08 is a Dual 4-B it Latch designed fo r general purpose storage applications in m edium speed digital systems. The 93 L 08 uses T T L technology and is T T L compatible. A ll inputs incorporate diode clamps to ground to reduce negative line transients. A ll outputs have
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93L08
24-LEAD
ScansUX992
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Untitled
Abstract: No abstract text available
Text: BU4S71 Single OR gate The BU4S71 is a 2-input positive logic OR gate. Dimensions Units : mm BU4S71 (SMP5) Features • low current consumption • wide operating voltage range • can directly drive 2 LpTTL inputs and a LS-TTL input „r •fl» ni Il B
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BU4S71
BU4S71
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Untitled
Abstract: No abstract text available
Text: LPTTL/SSI 9L04 LOW POWER HEX INVERTER CV DESCRIPTION — The low power TTL/SSI 9L04 consists of six TTL gates, each performing a single inversion function. Designed for low power, medium »peed operation, the 9L04 is very useful where • number of complement signets are desired simultaneously
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14-LEAD
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93L28
Abstract: ScansUX993
Text: LPTTL/MSI 93L28 LOW POWER DUAL 8-BIT SHIFT REGISTER DESCRIPTIO N — The LP T TL/M S I 9 3 L 28 is a m edium speed Serial Storage Element providing six teen bits o f storage in the fo rm o f tw o 8 -b it registers that w ill s h ift at greater than 5 MHz rates. The
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93L28
ScansUX993
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PIN14
Abstract: fairchild quad ScansUX997
Text: LPTTL/SSI 9L86 LOW POWER QUAD EXCLUSIVE OR GATE D E S C R IP T IO N — The Low Power TTL/SSI 9L86 consists of four Exclusive OR Gates. Designed for low power, medium speed operation, the 9L86 is useful in large number of code conversion, parity generation/checking and comparison applications. The exclusive OR gate produces an output when
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14-LEAD
9L86XM
9L86XC
PIN14
fairchild quad
ScansUX997
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ScansUX997
Abstract: No abstract text available
Text: LPTTL/SSI 9L54 LOW POWER AND-OR-INVERT GATE DESCRIPTION — The Low Power TTL/SSI 9L54 is a four wide, 2-2-2-3-input AND-OR-INVERT Gate. It is designed for low power and medium speed operation. TYPICAL POWER DISSIPATION OF 10 mW TYPICAL DELAY OF 25 ns INPUT CLAMP DIODES LIM IT HIGH SPEED TERMINATION EFFECTS
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MN5700
Abstract: N5700
Text: MN5700 200 °C 12 BIT A/D CONVERTER FEATURES • —55°C to +200°C Guaranteed Performance • Max Linearity Error ±0.05%FSR at +200°C • Max Accuracy Error ±1%FSR at +200°C • Low Power 311tnW • Internal Reference • 250 /¿sec Conversion Time • LPTTL-CMOS Compatible
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311mW
N5700
MN5700
N5700
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93L01
Abstract: ScansUX991
Text: LPTTL/MSI 93L01 LOW POWER ONE-OF-TEN DECODER D E S C R IP T IO N — The L P T T L /M S I 9 3 L 01 is a M ultipurpose Decoder designed to accept fo ur inputs and provide 10 m utu ally exclusive outputs. The circuit uses T T L technology and is com patible with
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93LOI
93L01
16-LEAD
ScansUX991
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2N5961
Abstract: 96L02 100C 2N5962 103pF ScansUX994
Text: LPTTL/MONOSTABLE 96L02 LOW POWER DUAL RETRIGGERABLE RESETTABLE MONOSTABLE MULTIVIBRATOR DESCRIPTIO N — The TTL/Monostable 96L02 is a low power Dual Retriggerable, Resettable Monostable Multivibrator which provides an output pulse whose duration and accuracy is a
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96L02
The96L02
2N5961
100C
2N5962
103pF
ScansUX994
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