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Catalog Datasheet	MFG & Type	Document Tags	PDF
P281 B01 Abstract: G187 Text: LogiCORE IP Processing System 7 v4.02a DS871 October 16, 2012 Product Specification Introduction LogiCORE IP Facts Table The Processing System 7 IP is the software interface around the Zynq Processing System. The Zynq -7000 family consists of an system-on-chip (SoC) style	Original	DS871 Zynq-7000 P281 B01 G187	PDF
Untitled Abstract: No abstract text available Text: LogiCORE IP AXI Interconnect v1.06.a DS768 December 18, 2012 Product Specification Introduction LogiCORE IP Facts Table The LogiCORE IP AXI Interconnect core connects one or more AXI memory-mapped master devices to one or more memory-mapped slave devices. The AXI	Original	DS768	PDF
AMBA AXI4 verilog code Abstract: ZYNQ-7000 BFM 20/ZYNQ-7000 BFM Text: LogiCORE IP AXI Bus Functional Models v3.00.a DS824 July 25, 2012 Product Specification Introduction LogiCORE IP Facts Table The Xilinx LogiCORE IP AXI Bus Functional Models (BFMs), developed for Xilinx by Cadence Design Systems, support the simulation of	Original	DS824 AMBA AXI4 verilog code ZYNQ-7000 BFM 20/ZYNQ-7000 BFM	PDF
Untitled Abstract: No abstract text available Text: 7 Series FPGAs Memory Interface Solutions v1.7 DS176 October 16, 2012 Advance Product Specification Introduction LogiCORE IP Facts Table The Xilinx 7 series FPGAs memory interface solutions cores provide high-performance connections to DDR3 and DDR2	Original	DS176	PDF
IBM Processor Local Bus PLB 64-Bit Architecture Abstract: data sheet DS400 DS400 Text: Processor Local Bus PLB v3.4 (v1.02a) DS400 April 24, 2009 Product Specification Introduction LogiCORE IP Facts The Xilinx 64-bit Processor Local Bus (PLB) consists of a bus control unit, a watchdog timer, and separate address, write, and read data path units with a a three-cycle only	Original	DS400 64-bit IBM Processor Local Bus PLB 64-Bit Architecture data sheet DS400	PDF
CORDIC v4.0 Abstract: FIX16 CORDIC in xilinx CORDIC SPARTAN-3E IC BA 3812 DATASHEET CORDIC system generator xilinx cordic design for fixed angle rotation cordic design for fixed angle of rotation cordic algorithm in matlab Text: CORDIC v4.0 DS249 April 24, 2009 Product Specification • Introduction The Xilinx LogiCORE IP CORDIC core implements a generalized coordinate rotational digital computer CORDIC algorithm. For use with Xilinx CORE Generator™ and Xilinx System Generator™ v11.1 or later.	Original	DS249 CORDIC v4.0 FIX16 CORDIC in xilinx CORDIC SPARTAN-3E IC BA 3812 DATASHEET CORDIC system generator xilinx cordic design for fixed angle rotation cordic design for fixed angle of rotation cordic algorithm in matlab	PDF
SPARTAN-3e microblaze Abstract: DS452 vhdl code for bram lmb bus timing Text: LMB BRAM Interface Controller v2.10b DS452 April 24, 2009 Product Specification Introduction LogiCORE Facts This document provides the design specification for the Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller. The LMB BRAM Interface Controller connects to an	Original	DS452 SPARTAN-3e microblaze vhdl code for bram lmb bus timing	PDF
asynchronous fifo vhdl xilinx Abstract: vhdl synchronous bus SRL16 DS449 microblaze Text: Fast Simplex Link FSL Bus (v2.11b) DS449 June 24, 2009 Product Specification Introduction LogiCORE Facts The FSL_V20 Fast Simplex Link (FSL) Bus is a uni-directional point-to-point communication channel bus used to perform fast communication between any	Original	DS449 asynchronous fifo vhdl xilinx vhdl synchronous bus SRL16 microblaze	PDF
DS429 Abstract: xc5vfx70t-ff1136-1 interrupt controller in vhdl code interrupt controller vhdl code interrupt controller vhdl code download interrupt vhdl XC5VFX70T-FF1136 SA-14-2525-00 Text: DCR Interrupt Controller v2.00a DS429 April 24, 2009 Product Specification Introduction LogiCORE Facts A DCR (Device Control Register Bus v29) Interrupt Controller (INTC) core is composed of a bus-centric wrapper containing the INTC core and a DCR interface.	Original	DS429 xc5vfx70t-ff1136-1 interrupt controller in vhdl code interrupt controller vhdl code interrupt controller vhdl code download interrupt vhdl XC5VFX70T-FF1136 SA-14-2525-00	PDF
cmps 10 Abstract: verilog code for pci express memory transaction "PCI Express" Encryption 00001111B XC5VLX20T "network interface cards" Text: Endpoint Block Plus v1.11 for PCI Express DS551 June 24, 2009 Product Specification Introduction The LogiCORE IP Endpoint Block Plus for PCI Express® core is a high-bandwidth, scalable, and reliable serial interconnect building block for use with Virtex®-5 LXT/SXT/FXT/TXT FPGA devices. The	Original	DS551 cmps 10 verilog code for pci express memory transaction "PCI Express" Encryption 00001111B XC5VLX20T "network interface cards"	PDF
vhdl code 64 bit FPU Abstract: vhdl code for march c algorithm vhdl code for pipelined matrix multiplication ieee floating point vhdl vhdl code for FFT 32 point ML403 UART ml403 vhdl code for matrix multiplication vhdl code for floating point matrix multiplication XILINX UART lite Text: APU Floating-Point Unit v3.1 March 11, 2008 Product Specification Introduction LogiCORE Facts The Xilinx Auxiliary Processor Unit APU Floating-Point Unit LogiCORETM is a single-precision floating-point unit designed for the PowerPCTM 405 embedded microprocessor of the VirtexTM-4 FX FPGA	Original		PDF
SRL16 Abstract: No abstract text available Text: LogiCORE IP Fixed Interval Timer FIT v1.01b DS451 April 19, 2010 Product Specification Introduction LogiCORE IP Facts The LogiCORE IP FIT core is a peripheral that generates a strobe (interrupt) signal at fixed intervals and is not attached to any bus. The Fixed Interval Timer (FIT)	Original	DS451 SRL16	PDF
PLL variable frequency generator Abstract: QPro Virtex 4 Hi-Rel PLL 02A DS614 fpga 3 phase inverter DS6-14 MMCM Text: Clock Generator DS614 April 19, 2010 Product Specification Introduction LogiCORE IP Facts Core Specifics The Clock Generator module provides clocks according to system wide clock requirements. Virtex -6/6CX, Spartan®-6, Spartan-3A/3A DSP, Spartan-3, Spartan-3E, Automotive	Original	DS614 PLL variable frequency generator QPro Virtex 4 Hi-Rel PLL 02A fpga 3 phase inverter DS6-14 MMCM	PDF
3S1000FG456-4C Abstract: PCI64 vhdl code for 8 bit parity generator vhdl code for parity checker 2-S200 Text: LogiCORE PCI64 Interface v3.0 DS205 April 14, 2003 Introduction LogiCORE Facts With the Xilinx LogiCORE PCI Interface, a designer can build a customized PCI 2.3-compliant core with the highest possible sustained performance, 528 Mbytes/sec. Features •	Original	PCI64 DS205 64-bit, 32-bit 64/32-bit PCI64/33 3S1000FG456-4C vhdl code for 8 bit parity generator vhdl code for parity checker 2-S200	PDF

virtex ucf file 6 Abstract: vhdl code for parity checker vhdl code for 3 bit parity checker VME to isa bridge vme bus specification vhdl verilog code for pci to pci bridge verilog code for pci express vhdl code for multiplexer 64 to 1 using 8 to 1 virtex user guide 1999 PCI64 Text: PCI64 Virtex Interface V 3.0 November 1, 1999 Data Sheet R LogiCORE Facts Core Specifics Xilinx Inc. 2100 Logic Drive San Jose, CA 95124 Phone: +1 408-559-7778 Fax: +1 408-377-3259 E-mail: Techsupport: support.xilinx.com Feedback: logicore@xilinx.com URL:	Original	PCI64 64-bit, virtex ucf file 6 vhdl code for parity checker vhdl code for 3 bit parity checker VME to isa bridge vme bus specification vhdl verilog code for pci to pci bridge verilog code for pci express vhdl code for multiplexer 64 to 1 using 8 to 1 virtex user guide 1999	PDF
XC2064 Abstract: XC4028XLA verilog code for fir filter new ieee programs in vhdl and verilog SCR FIR 3 D XC3090 XC4005 XC4005XL XC5210 XC8106 Text: CORE Generator System User Guide V1.5.2i XACT, XC2064, XC3090, XC4005, XC5210, XC8106, XC-DS-501, FPGA Architect, FPGA Foundry, LogiCORE, Timing Wizard, and Trace are registered trademarks of Xilinx. All XC-prefix product designations, AllianceCore, Alliance Series, BITA, CLC,	Original	XC2064, XC3090, XC4005, XC5210, XC8106, XC-DS-501, XC4028EX PG299 XC2064 XC4028XLA verilog code for fir filter new ieee programs in vhdl and verilog SCR FIR 3 D XC3090 XC4005 XC4005XL XC5210 XC8106	PDF
XC6200 Abstract: lola XC6216 vhdl synchronous bus HQ240 PQ160 PQ208 XC4013E XC4020E Text: New LogiCORE PCI Target Eases System Integration The new LogiCORE PCI Slave target- improved, and the new version is more robust TM only v1.1 has been shipped to all LogiCore PCI owners with current maintenance agreements. This updated release will further	Original	XC4020E XC4013E HQ240 PQ208 PQ160 PCI-XC6200 XC6216 XC6200 lola vhdl synchronous bus HQ240 PQ160 PQ208 XC4013E XC4020E	PDF
door bell Abstract: sb01 BG432 PCI32 SB03 register based fifo xilinx pci initiator in verilog Text: 2 Synthesizable PCI Bridge Designs June, 1998 Data Sheet General Description R Part of or all of the design is available at no cost to all registered LogiCORE PCI32 Interface customers, who can download it from the LogiCORE PCI Lounge at Xilinx Inc. 2100 Logic Drive	Original	PCI32 door bell sb01 BG432 SB03 register based fifo xilinx pci initiator in verilog	PDF
LTE antenna design Abstract: xilinx lte XMP041 3621-1 Text: LogiCORE IP LTE RACH Detector v1.0 XMP041 April 19, 2010 Product Brief Introduction Overview 'The Xilinx LTE RACH detector core decodes P-RACH data encoded according to the 3GPP TS 36.211 v9.0 2009-12 Physical Channels and Modulation specification. The LTE RACH detector core provides a RACH detection solution for the 3GPP TS 36.211 v9.0.0 (2009-12)	Original	XMP041 LTE antenna design xilinx lte 3621-1	PDF
virtex 5 fpga based image processing Abstract: DSP48A DSP48A1 DSP48E DSP48E1 Xilinx ISE Design Suite XICSI Text: LogiCORE IP Image Characterization v1.1 DS727 September 21, 2010 Product Specification Introduction LogiCORE IP Facts Table The Xilinx Image Characterization LogiCORE IP calculates important statistical data for video input streams. The Image Characterization LogiCORE is an	Original	DS727 1080p virtex 5 fpga based image processing DSP48A DSP48A1 DSP48E DSP48E1 Xilinx ISE Design Suite XICSI	PDF
ISO 11898-1 Abstract: bosch can 2.0B Spartan-3an DSP/VIRTEX ACFB Text: CAN v1.5 DS265 August 8, 2007 Product Specification Introduction LogiCORE Facts The LogiCORE Controller Area Network CAN product specification describes the architecture and features of the Xilinx CAN controller core and the functionality of the various registers in the design. In	Original	DS265 ISO 11898-1 bosch can 2.0B Spartan-3an DSP/VIRTEX ACFB	PDF
DS504 Abstract: LocalLink Text: SPI-3 Link Layer v5.1 DS504 August 8, 2007 Product Specification Introduction LogiCORE Facts The Xilinx LogiCORE SPI-3 Link Layer core provides a complete, pre-engineered solution that is fully compatible with the OIF-SPI3-01.0 System Packet Interface Level-3 standard. Implementation Agreement. This	Original	DS504 OIF-SPI3-01 LocalLink	PDF
RX-6 TX-6 Abstract: DS209 IXP2800 ML450 ML550 VIRTEX-5 DDR PHY DCM02 Text: SPI-4.2 v8.4 DS209 August 8, 2007 Product Specification Introduction LogiCORE Facts Core Specifics Device Family Alignment Type Performance Mbps /Speed LUT/Flop Pairs 64-bit static 622–700/-1,-2,-3 Rx: 2000 Tx: 2600 Rx: 6 Tx: 6 128-bit static 622–700/-1,-2,-3	Original	DS209 64-bit OIF-SPI4-02 RX-6 TX-6 IXP2800 ML450 ML550 VIRTEX-5 DDR PHY DCM02	PDF
Untitled Abstract: No abstract text available Text: RapidIO Logical I/O and Transport Layer Interface v4.1 DS242 February 15, 2007 Product Specification Introduction LogiCORE Facts The LogiCORE RapidIO™ Logical (I/O) and Transport Layer interface is optimized for Virtex™-5 LXT/SXT, Virtex-4 FX and Virtex-II Pro FPGAs, and is compliant with	Original	DS242 5VLX30T 4VFX20 2VP20	PDF

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LOGICORE Search Results

LOGICORE Datasheets Context Search

P281 B01

Untitled

AMBA AXI4 verilog code

Untitled

IBM Processor Local Bus PLB 64-Bit Architecture

CORDIC v4.0

SPARTAN-3e microblaze

asynchronous fifo vhdl xilinx

DS429

cmps 10

vhdl code 64 bit FPU

SRL16

PLL variable frequency generator

3S1000FG456-4C

virtex ucf file 6

XC2064

XC6200

door bell

LTE antenna design

virtex 5 fpga based image processing

ISO 11898-1

DS504

RX-6 TX-6

Untitled