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    LOGIC OR GATE 3 INPUTS Search Results

    LOGIC OR GATE 3 INPUTS Result Highlights (6)

    Part ECAD Model Manufacturer Description Download Buy
    TB67H481FTG Toshiba Electronic Devices & Storage Corporation Stepping and Brushed Motor Driver /Bipolar Type / Vout(V)=50 / Iout(A)=3.0 / IN input type / VQFN32 Visit Toshiba Electronic Devices & Storage Corporation
    DCL541A01 Toshiba Electronic Devices & Storage Corporation Digital Isolator / VDD=2.25~5.5V / 150Mbps / 4 channel(F:R=3:1) / Default Output Logic: Low / Input disable Visit Toshiba Electronic Devices & Storage Corporation
    DCL541B01 Toshiba Electronic Devices & Storage Corporation Digital Isolator / VDD=2.25~5.5V / 150Mbps / 4 channel(F:R=3:1) / Default Output Logic: High / Input disable Visit Toshiba Electronic Devices & Storage Corporation
    TLX9188 Toshiba Electronic Devices & Storage Corporation Photocoupler (phototransistor output), DC input, 3750 Vrms, SO6, Automotive Visit Toshiba Electronic Devices & Storage Corporation
    TB67H480FNG Toshiba Electronic Devices & Storage Corporation Stepping Motor Driver/Unipolar Type/Vout(V)=50/Iout(A)=2.5/ PHASE input type Visit Toshiba Electronic Devices & Storage Corporation
    TB67H481FNG Toshiba Electronic Devices & Storage Corporation Stepping Motor Driver/Unipolar Type/Vout(V)=50/Iout(A)=2.5/ IN input type Visit Toshiba Electronic Devices & Storage Corporation

    LOGIC OR GATE 3 INPUTS Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    cd74hc4075

    Abstract: CD74HC4075E
    Text: CD74HC4075, CD74HCT4075 S E M I C O N D U C T O R High Speed CMOS Logic Triple 3-Input OR Gate August 1997 Features Description • Buffered Inputs The Harris CD74HC4075, CD74HCT4075 logic gates utilize silicon-gate CMOS technology to achieve operating speeds


    Original     		PDF CD74HC4075, CD74HCT4075 CD74HCT4075 74HCT 1-800-4-HARRIS cd74hc4075 CD74HC4075E

    C4075

    Abstract: 74HCT 74LS CD54HC4075H CD74HC4075 CD74HC4075E CD74HC4075M CD74HCT4075
    Text: [ /Title CD74H C4075, CD74H CT4075 /Subject (High Speed CMOS Logic Triple 3Input CD74HC4075, CD74HCT4075 Data sheet acquired from Harris Semiconductor SCHS210 High Speed CMOS Logic Triple 3-Input OR Gate August 1997 Features Description • Buffered Inputs


    Original     		PDF CD74H C4075, CT4075) CD74HC4075, CD74HCT4075 SCHS210 CD74HCT4075 74HCT C4075 74LS CD54HC4075H CD74HC4075 CD74HC4075E CD74HC4075M

    DIN159

    Abstract: PLS159AN OEA159 PLS159 PLS159A PLS159AA CK159
    Text: Philips Semiconductors Programmable Logic Devices Product specification Programmable logic sequencer 16 x 45 × 12 DESCRIPTION PLS159A FEATURES The PLS159A is a 3-State output, registered logic element combining AND/OR gate arrays with clocked J-K flip-flops. These J-K


    Original     		PDF PLS159A PLS159A DIN159 NIN159 OEA159 OEB159 EXOR159 DIN159 PLS159AN OEA159 PLS159 PLS159AA CK159

    74AUP1G0832

    Abstract: 74AUP1G0832GF 74AUP1G0832GM 74AUP1G0832GW
    Text: 74AUP1G0832 Low-power 3-input AND-OR gate Rev. 3 — 5 October 2010 Product data sheet 1. General description The 74AUP1G0832 provides the Boolean function: Y = A x B + C. The user can choose the logic functions OR, AND and AND-OR. All inputs can be connected to VCC or GND.


    Original     		PDF 74AUP1G0832 74AUP1G0832 74AUP1G0832GF 74AUP1G0832GM 74AUP1G0832GW

    74AUP1G3208

    Abstract: 74AUP1G3208GF 74AUP1G3208GM 74AUP1G3208GW JESD22-A114E
    Text: 74AUP1G3208 Low-power 3-input OR-AND gate Rev. 02 — 3 July 2009 Product data sheet 1. General description The 74AUP1G3208 provides the Boolean function: Y = A + B x C. The user can choose the logic functions OR, AND and OR-AND. All inputs can be connected to VCC or GND.


    Original     		PDF 74AUP1G3208 74AUP1G3208 74AUP1G3208GF 74AUP1G3208GM 74AUP1G3208GW JESD22-A114E

    74AUP1G0832

    Abstract: 74AUP1G0832GF 74AUP1G0832GM 74AUP1G0832GW JESD22-A114E
    Text: 74AUP1G0832 Low-power 3-input AND-OR gate Rev. 02 — 3 July 2009 Product data sheet 1. General description The 74AUP1G0832 provides the Boolean function: Y = A x B + C. The user can choose the logic functions OR, AND and AND-OR. All inputs can be connected to VCC or GND.


    Original     		PDF 74AUP1G0832 74AUP1G0832 74AUP1G0832GF 74AUP1G0832GM 74AUP1G0832GW JESD22-A114E

    Untitled

    Abstract: No abstract text available
    Text: [ /Title CD74H C4075, CD74H CT4075 /Subject (High Speed CMOS Logic Triple 3Input CD54HC4075, CD74HC4075, CD54HCT4075, CD74HCT4075 Data sheet acquired from Harris Semiconductor SCHS210F High-Speed CMOS Logic Triple 3-Input OR Gate August 1997 - Revised August 2003


    Original     		PDF CD54HC4075, CD74HC4075, CD54HCT4075, CD74HCT4075 SCHS210F HC4075 HCT4075 CD74H C4075,

    C4075

    Abstract: CD54HC4075 CD54HC4075F3A CD54HCT4075 CD74HC4075 CD74HCT4075 HC4075
    Text: [ /Title CD74H C4075, CD74H CT4075 /Subject (High Speed CMOS Logic Triple 3Input CD54HC4075, CD74HC4075, CD54HCT4075, CD74HCT4075 Data sheet acquired from Harris Semiconductor SCHS210F High-Speed CMOS Logic Triple 3-Input OR Gate August 1997 - Revised August 2003


    Original     		PDF CD74H C4075, CT4075) CD54HC4075, CD74HC4075, CD54HCT4075, CD74HCT4075 SCHS210F HC4075 C4075 CD54HC4075 CD54HC4075F3A CD54HCT4075 CD74HC4075 CD74HCT4075

    CD54HC4075F3A

    Abstract: C4075 CD54HC4075 CD54HCT4075 CD74HC4075 CD74HCT4075 HC4075
    Text: [ /Title CD74H C4075, CD74H CT4075 /Subject (High Speed CMOS Logic Triple 3Input CD54HC4075, CD74HC4075, CD54HCT4075, CD74HCT4075 Data sheet acquired from Harris Semiconductor SCHS210F High-Speed CMOS Logic Triple 3-Input OR Gate August 1997 - Revised August 2003


    Original     		PDF CD74H C4075, CT4075) CD54HC4075, CD74HC4075, CD54HCT4075, CD74HCT4075 SCHS210F HC4075 CD54HC4075F3A C4075 CD54HC4075 CD54HCT4075 CD74HC4075 CD74HCT4075

    C4075

    Abstract: HC4075 CD54HC4075 CD54HC4075F3A CD54HCT4075 CD74HC4075 CD74HCT4075
    Text: [ /Title CD74H C4075, CD74H CT4075 /Subject (High Speed CMOS Logic Triple 3Input CD54HC4075, CD74HC4075, CD54HCT4075, CD74HCT4075 Data sheet acquired from Harris Semiconductor SCHS210F High-Speed CMOS Logic Triple 3-Input OR Gate August 1997 - Revised August 2003


    Original     		PDF CD74H C4075, CT4075) CD54HC4075, CD74HC4075, CD54HCT4075, CD74HCT4075 SCHS210F HC4075 C4075 CD54HC4075 CD54HC4075F3A CD54HCT4075 CD74HC4075 CD74HCT4075

    Untitled

    Abstract: No abstract text available
    Text: [ /Title CD74H C4075, CD74H CT4075 /Subject (High Speed CMOS Logic Triple 3Input CD54HC4075, CD74HC4075, CD54HCT4075, CD74HCT4075 Data sheet acquired from Harris Semiconductor SCHS210G High-Speed CMOS Logic Triple 3-Input OR Gate August 1997 - Revised June 2006


    Original     		PDF CD74H C4075, CT4075) CD54HC4075, CD74HC4075, CD54HCT4075, CD74HCT4075 SCHS210G HC4075

    Untitled

    Abstract: No abstract text available
    Text: [ /Title CD74H C4075, CD74H CT4075 /Subject (High Speed CMOS Logic Triple 3Input CD54HC4075, CD74HC4075, CD54HCT4075, CD74HCT4075 Data sheet acquired from Harris Semiconductor SCHS210G High-Speed CMOS Logic Triple 3-Input OR Gate August 1997 - Revised June 2006


    Original     		PDF CD74H C4075, CT4075) CD54HC4075, CD74HC4075, CD54HCT4075, CD74HCT4075 SCHS210G HC4075

    C4075

    Abstract: CD54HC4075 CD54HC4075F3A CD54HCT4075 CD74HC4075 CD74HCT4075 HC4075
    Text: [ /Title CD74H C4075, CD74H CT4075 /Subject (High Speed CMOS Logic Triple 3Input CD54HC4075, CD74HC4075, CD54HCT4075, CD74HCT4075 Data sheet acquired from Harris Semiconductor SCHS210F High-Speed CMOS Logic Triple 3-Input OR Gate August 1997 - Revised August 2003


    Original     		PDF CD74H C4075, CT4075) CD54HC4075, CD74HC4075, CD54HCT4075, CD74HCT4075 SCHS210F HC4075 C4075 CD54HC4075 CD54HC4075F3A CD54HCT4075 CD74HC4075 CD74HCT4075

    Untitled

    Abstract: No abstract text available
    Text: [ /Title CD74H C4075, CD74H CT4075 /Subject (High Speed CMOS Logic Triple 3Input CD54HC4075, CD74HC4075, CD54HCT4075, CD74HCT4075 Data sheet acquired from Harris Semiconductor SCHS210G High-Speed CMOS Logic Triple 3-Input OR Gate August 1997 - Revised June 2006


    Original     		PDF CD54HC4075, CD74HC4075, CD54HCT4075, CD74HCT4075 SCHS210G HC4075 HCT4075 CD74H C4075,

    cd74HC32

    Abstract: cd74hct32
    Text: P *3 3 S CD54HCT32, CD74HC32, CD74HCT32 High Speed CMOS Logic Quad 2-Input OR Gate September 1997 Features Description • Typical Propagation Delay: 7ns at Vcc = 5V, C L = 15pF, Ta = 25°C The Harris CD74HC32, CD74HCT32 contain four 2-input OR gates in one package. Logic gates utilize silicon gate CMOS


    OCR Scan     		PDF CD54HCT32, CD74HC32, CD74HCT32 CD74HCT32 74HCT cd74HC32

    Untitled

    Abstract: No abstract text available
    Text: C2MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC TC4071BP/BF/BFNJC4072BP/BF TC4075BP/BF TC4071B QUAD 2 INPUT OR GATE TC4072B DUAL 4 INPUT OR GATE TC4075B TRIPLE 3 INPUT OR GATE TC4071B, TC4075BP / BF and TC4072BP / BF are positive logic OR gates w ith tw o inputs, three inputs and fo ur inputs


    OCR Scan     		PDF TC4071BP/BF/BFNJC4072BP/BF TC4075BP/BF TC4071B TC4072B TC4075B TC4071B, TC4075BP TC4072BP TC4071B

    10119F

    Abstract: 10119N
    Text: 10119 Signetics Gate 4-W ide 4-3-3-3-lnput OR-AND Gate Product Specification ECL Products DESCRIPTION The 10119 is a 4-wide 4-3-3-3-lnput ORAND Gate designed for use in data control as a general purpose logic ele­ ment. All unused inputs can be left open


    OCR Scan     		PDF 10119N 10119F 800mVp-p 500ns 10119F 10119N

    Untitled

    Abstract: No abstract text available
    Text: CD74HC4075, CD74HCT4075 HARRIS S E M I C O N D U C T O R High Speed CMOS Logic Triple 3-Input OR Gate August 1997 Features • Description Buffered Inputs The Harris CD74HC4075, CD74HCT4075 logic gates utilize silicon-gate CMOS technology to achieve operating speeds


    OCR Scan     		PDF CD74HC4075, CD74HCT4075 CD74HCT4075 74HCT 1-800-4-HARRIS

    Untitled

    Abstract: No abstract text available
    Text: S CD74HC4075, CD74HCT4075 Semiconductor y High Speed CMOS Logic Triple 3-Input OR Gate August 1997 Features Description • Buffered Inputs The Harris CD74HC4075, CD74HCT4075 logic gates utilize silicon-gate CMOS technology to achieve operating speeds similar to LSTTL gates with the low power consumption of


    OCR Scan     		PDF CD74HC4075, CD74HCT4075 CD74HCT4075 74HCT

    Untitled

    Abstract: No abstract text available
    Text: MOTOROLA DUAL 2-WIDE 2-3-INPUT "OR-AND/OR-AND-INVERT" GATE DUAL 2-WIDE 2-3-INPUT "OR-AND/OR-AND-INVERT" GATE The MC10117 is a general purpose logic element designed for use in data control, such as digital multiplexing or data distri­ bution. Pin 9 is common to both gates.


    OCR Scan     		PDF MC10117

    TC4072B

    Abstract: TC4075BP TC4072BP TC4071B
    Text: TC4071BP/BF/ BFN, TC4072BP/BF C2MOS DIGITAL INTEGRATED CIRCUIT T P ^ n 7 K B D / B C SILICON MONOLITHIC I IrrU / JD I7 Dr TC4071B QUAD 2 INPUT OR GATE TC4072B DUAL 4 INPUT OR GATE TC4075B TRIPLE 3 INPUT OR GATE TC4071B, TC4075BP/ BF and TC4072BP / BF are positive logic


    OCR Scan     		PDF TC4071BP/BF/ TC4072BP/BF TC4071B TC4072B TC4075B TC4071B, TC4075BP/ TC4072BP TC4071B TC4071B) TC4075BP

    pls157

    Abstract: No abstract text available
    Text: Product specification Philips Semiconductors Programmable Logic Devices Programmable logic sequencer 16x45x12 DESCRIPTION PLS157 PIN CONFIGURATIONS FEATURES The PLS157 is a 3-State output, registered logic element combining AND/OR gate arrays with clocked J-K flip-flops. These J-K


    OCR Scan     		PDF 16x45x12) PLS157 PLS157

    PLS179N

    Abstract: No abstract text available
    Text: Product spécification Philips Semiconductors Programmable Logic Devices Programmable logic sequencer 20x45x12 DESCRIPTION PLS179 PIN CONFIGURATIONS FEATURES The PLS179 is a 3-State output, registered logic element combining AND/OR gate arrays with docked J-K flip-flops. These J-K


    OCR Scan     		PDF 20x45x12) PLS179 PLS179 PLS179N

    MF522

    Abstract: mod 8 using jk flipflop PLS179A PLS179N q302-q1
    Text: Philips Semiconductors Programmable Logic Devices Product specification Programm able logic sequencer 20 x 45 x 12 DESCRIPTION PLS179 FEATURES The PLS179 is a 3-State output, registered logic efement combining AND/OR gate arrays with clocked J-K flip-flops. These J-K


    OCR Scan     		PDF PLS179 PLS179 20x45x12) MF522 mod 8 using jk flipflop PLS179A PLS179N q302-q1