LMU112JC25 Search Results

LMU112JC25 Datasheets (1)

Part	ECAD Model	Manufacturer	Description	Curated	Type	PDF
LMU112JC25		Logic Devices	12 x 12-bit Parallel Multiplier		Original	PDF

LMU112JC25 Datasheets Context Search

Catalog Datasheet	MFG & Type	PDF	Document Tags
LMU112 Abstract: LMU112JC25 LMU112JC50 LMU112PC25 LMU112PC50 MPY112K Text: LMU112 LMU112 DEVICES INCORPORATED 12 x 12-bit Parallel Multiplier 12 x 12-bit Parallel Multiplier DEVICES INCORPORATED FEATURES ❑ ❑ ❑ ❑ 25 ns Worst-Case Multiply Time Low Power CMOS Technology Replaces Fairchild MPY112K Two’s Complement or Unsigned	Original	PDF	LMU112 12-bit MPY112K 48-pin 52-pin LMU112 LMU112JC25 LMU112JC50 LMU112PC25 LMU112PC50 MPY112K
LMU112 Abstract: LMU112DC50 LMU112DC60 LMU112PC25 LMU112PC50 LMU112PC60 MPY112K Text: LMU112 LMU112 DEVICES INCORPORATED 12 x 12-bit Parallel Multiplier 12 x 12-bit Parallel Multiplier DEVICES INCORPORATED FEATURES ❑ ❑ ❑ ❑ ❑ ❑ ❑ DESCRIPTION 25 ns Worst-Case Multiply Time Low Power CMOS Technology Replaces TRW MPY112K Two’s Complement or Unsigned	Original	PDF	LMU112 12-bit MPY112K MIL-STD-883, 48-pin 52-pin LMU112 LMU112DC50 LMU112DC60 LMU112PC25 LMU112PC50 LMU112PC60 MPY112K
LMU112 Abstract: LMU112JC25 LMU112JC50 LMU112PC25 LMU112PC50 MPY112K R13NC 212109 Text: LMU112 LMU112 DEVICES INCORPORATED 12 x 12-bit Parallel Multiplier 12 x 12-bit Parallel Multiplier DEVICES INCORPORATED FEATURES ❑ ❑ ❑ ❑ 25 ns Worst-Case Multiply Time Low Power CMOS Technology Replaces Fairchild MPY112K Two’s Complement or Unsigned	Original	PDF	LMU112 12-bit MPY112K 48-pin 52-pin LMU112 LMU112JC25 LMU112JC50 LMU112PC25 LMU112PC50 MPY112K R13NC 212109
B1016 Abstract: LMU11250 Text: LMU112 12 x 12-bit Parallel Multiplier □ FV IC E S IN C O R P Q R A T F D FEATURES □ 25 ns W orst-Case M ultiply Time □ Low Power CMOS Technology □ Replaces Fairchild M PY112K □ Tw o's Complement or Unsigned Operands □ Three-State Outputs □ Package Styles Available:	OCR Scan	PDF	LMU112 12-bit LMU112 MPY112K. LMU112JC50 LMU112JC25 LMU112PC50 LMU112PC25 B1016 LMU11250
Untitled Abstract: No abstract text available Text: LMU112 12 x 12-bit Parallel Multiplier D E V IC E S IN C O R P O R A T E D DESCRIPTION FEATURES □ 25 ns W orst-Case M ultiply Time □ Low Power CMOS Technology □ Replaces Fairchild M PY112K □ Tw o's Complement or Unsigned Operands □ Three-State Outputs	OCR Scan	PDF	LMU112 12-bit PY112K 48-pin 52-pin LMU112 MPY112K. LMU112JC50
Untitled Abstract: No abstract text available Text: . o <13 »nil CI» LMU112 12 x 12-bit Parallel M ultip lie r T he L M U 112 is a high-speed, low p ow er 12-bit parallel m ultiplier bu ilt using ad vanced C M O S technology. The L M U 112 is pin and functionally com patible w ith T R W 's M PY112K . □ 25 ns W orst-C ase M u ltiply Tim e	OCR Scan	PDF	48-pin 52-pin LMU112 12-bit PY112K LMU112JC60 LMU112JC50 LMU112JC25 LMU112PC60
Untitled Abstract: No abstract text available Text: I M l 1119 - i; r LMU112 , 12 x 12-bit Parallel Multiplier DEVICES INCORPORATED FEATURES_ _ □ 25 ns W orst-Case M ultiply Time □ Low Power CMOS Technology □ Replaces TRW M PY112K □ Tw o's Complement or Unsigned Operands □ Three-State Outputs	OCR Scan	PDF	LMU112 12-bit PY112K MIL-STD-883, 48-pin 52-pin LMU112
Untitled Abstract: No abstract text available Text: LM U112 12 x 12-bit Parallel Multiplier FEATURES □ 25 ns W orst-Case Multiply Time □ Low Power CMOS Technology □ Replaces TRW MPY112K □ Tw o's Complement or Unsigned Operands □ Three-State Outputs □ Available 100% Screened to MIL-STD-883, Class B	OCR Scan	PDF	12-bit MPY112K MIL-STD-883, 48-pin 52-pin LMU112 LMU112 MPY112K.
R238 Abstract: No abstract text available Text: ¿oogç LMU112 12 x 12-bit Parallel Multiplier D E V IC E S IN C O R P O R A T E D FEATURES □ □ □ □ 25 ns Worst-Case Multiply Time Low Power CMOS Technology Replaces TRW MPY112K Tw o's Complement or Unsigned Operands □ Three-State Outputs □ Available 100% Screened to	OCR Scan	PDF	LMU112 12-bit MPY112K MIL-STD-883, 48-pin 52-pin R238