C 12 PH
Abstract: No abstract text available
Text: 3QE D E C ELECTRONICS INC • LM27SES 'üOSTbbO 1 o HIGH SPEED 8P IN PHOTO CO U PLER P A C K A G E D IM E N S IO N S FEATURES U n it: m m l • High Speed Response O J p s T Y P . 9.621 0.5 3 n 7 n • High Isolation Voltage 2 500 V r m-J- 6 n 5 r • Compact, Dual In-Line Package
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LM27SES
42752S
C 12 PH
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uPD30412L
Abstract: UPD30412LRJ250
Text: CHAPTER 1 1.1 G EN ERA L Introduction The /j PD30412, 30412L V r4400MC processor supports interfaces to secondary cache, system interlace, and boot time mode control. This document describes the connection and operation of each of these interfaces. Remark
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uPD30412
uPD30412L
Vr4400MC)
r4000TM
400TM
IEU-1344)
000PC
r4400PCTM
IEU-1329)
400SC
UPD30412LRJ250
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Nec concurrent rdram
Abstract: concurrent rdram NEC concurrent rdram CI 7424
Text: PRELIMINARY DATA SHEET NEC MOS INTEGRATED CIRCUIT |xPD488170 18M bit Rambus DRAM 1 Mword x 9bit x 2bank Description |J The 18-Megabit Rambus DRAM (RDRAM™) Is an extremely-high-speed CMOS DRAM organized a sJM w o r llb y 9 bits and capable of bursting up to 256 bytes of data at 2 ns per byte. The use of Rambus S igrgling L o 1 |l% |S L )
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xPD488170
18-Megabit
bM275
ED-7424)
LM27SES
Nec concurrent rdram
concurrent rdram NEC
concurrent rdram
CI 7424
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100484
Abstract: 100A484 100474 D-20 100476LL
Text: N E C ELECTRONICS INC blE D • ÆJJ W NEC Electronics Inc. L4E752S GG3534fl IGT « N E C E #iPD10500 262,144 X 1-Bit 10K BiCMOS ECL RAM T ' t t » -o 2 3 - ¿>5 - Description Pin Configuration The jiPD10500 is a very high-speed BiCMOS RAM with a 10K ECL interface. Its unique design uses blended
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uPD10500
300-mil,
24-pin
L4E752S
GG3534fl
iPD10500
L427525
00474A
100474E
100484
100A484
100474
D-20
100476LL
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78p334
Abstract: PD78310 uPD78P334 IC 64256 UPD78312 78P334LQ PKW-1100 manual 23 tfk 101 5253 1007 UPD78320
Text: DATA SHEET MOS INTEGRATED CIRCUIT ¿¿PD78330, 78334 16/8 BIT SINGLE-CHIP M ICRO CO M PUTER The ¿iPD78334 is a product of the 78K/III series. It contains a 16-bit high-performance CPU. The /¿PD78334 has a more powerful function for the real-time pulse unit and contains more extended internal
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uPD78330
uPD78334
iPD78334
78K/III
16-bit
PD78334
/iPD78322.
32K-byte
1024-byte
78p334
PD78310
uPD78P334
IC 64256
UPD78312
78P334LQ
PKW-1100 manual
23 tfk 101
5253 1007
UPD78320
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Untitled
Abstract: No abstract text available
Text: DATA SHEET / MOS INTEGRATED CIRCUIT UPD78094,78095,78096,78098A 8-BIT SINGLE-CHIP MICROCONTROLLERS DESCRIPTION The ¿¿PD78094,78095,78096,78098Aare members of the /¿PD78098 subseries of the 78K/0 series of microcontrollers. Besides a high-speed and high-performance CPU, each microcontroller has on-chip ROM, RAM, I/O ports, an lEBus
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UPD78094
8098A
PD78094
78098Aare
PD78098
78K/0
PD78P098A)
/PD78P098A
b427525
DDfl317b
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D882 NEC
Abstract: nec d882 nec d381 nec d882 p UPD8255AC-5 NEC DB82 CD1800 UPD8085AC NEC 8255 USART 8251
Text: N E ”c ~ E L E C T R O Ñ Í C S _lÑC _liö ’d Ê J t,MS?SaS D D l hfin □ D 7"~77-/3 NEC Electronics Inc. NEC ADVAN CED PRODUCT INFORMATION U S E R ’S MANUAL Ju n e 1985 / 3 Speech Recognition LSI Set T h e Information contained in this docum ent is being issued in advance of the production cy cle for the device. The
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PD481850GF
Abstract: D481850
Text: DATA SHEET NEC MOS INTEGRATED CIRCUIT /¿PD 481850 8M-bit Synchronous GRAM Description The iiPD481850 is a synchronous graphics memory SGRAM organized as 131,072 words x 32 bits x 2 banks random access port. This device can operate up to 100 MHz by using synchronous interface. Also, it has 8-column Block Write function
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uPD481850
100-pin
-613i8
-787io
S1000F-W-JBT
b4E7525
DDb3T73
pPD481850.
/1PD481850GF-JBT:
PD481850GF
D481850
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3TH43
Abstract: No abstract text available
Text: D A T A S H EET NEC MOS INTEGRATED CIRCUIT 4-BIT SINGLE-CHIP MICROCOMPUTER DESCRIPTION /xPD75108A is a 4-bit single-chip CMOS microcomputer having a data processing capability comparable to that of an 8-bit microcomputer. Operating at high speeds, the microcomputer allows data to be manipulated
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uPD75108A
jiPD75108A
//PD75108A:
IE-75000-R
IE-75001-R
IE-75000-R-EM"
EP-75108AGC-R
IEV-9200GC-64
RA75X
3TH43
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d 65632
Abstract: 65612 nec L302 CMOS Transmission gate Specifications nec cmos CMOS-5 NEC OPENCAD CMOS Block library 700-207
Text: CMOS-6/ 6A/6V/6X 1.0-MICRON CMOS GATE ARRAYS NEC NEC Electronics Inc. February 1995 Description Figure 1. Sample CMOS-6/6A/6 V/6X Packages NEC’s CMOS-6 gate array families CMOS-6, CMOS6A, CMOS-6V and CMOS-6X are high performance, sub-micron effective channel length CMOS products
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Untitled
Abstract: No abstract text available
Text: PRELIMINARY DATA SHEET MOS INTEGRATED CIRCUIT juPD42S18165L, 4218165L 3.3 V OPERATION 16 M BIT DYNAMIC RAM 1 M-WORD BY 16-BIT, HYPER PAGE MODE, BYTE READ/WRITE MODE Description The ftPD42S18165L, 4218165L are 1 048 576 words by 16 bits CMOS dynamic RAMs with optional hyper page
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juPD42S18165L
4218165L
16-BIT,
ftPD42S18165L,
4218165L
/iPD42S18165L,
50-pin
42-pin
fiPD42S18165L-A70,
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Untitled
Abstract: No abstract text available
Text: CHAPTER 5 IN ST R U C T IO N 5.1 Instruction Format The V850 family has two types of instruction formats: 16-bit and 32-bit. The 16-bit instructions include binary operation, control, and conditional branch instructions, and the 32-bit instructions include load/store, jump, and
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16-bit
32-bit.
32-bit
16tem
b427525
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