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    LM 4050 IC Search Results

    LM 4050 IC Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    74HC4053FT Toshiba Electronic Devices & Storage Corporation CMOS Logic IC, SPDT(1:2)/Analog Multiplexer, TSSOP16B, -40 to 125 degC Visit Toshiba Electronic Devices & Storage Corporation
    7UL2T125FK Toshiba Electronic Devices & Storage Corporation One-Gate Logic(L-MOS), Buffer, SOT-765 (US8), -40 to 85 degC Visit Toshiba Electronic Devices & Storage Corporation
    7UL2T126FK Toshiba Electronic Devices & Storage Corporation One-Gate Logic(L-MOS), Buffer, SOT-765 (US8), -40 to 85 degC Visit Toshiba Electronic Devices & Storage Corporation
    74HC4051FT Toshiba Electronic Devices & Storage Corporation CMOS Logic IC, SP8T(1:8)/Analog Multiplexer, TSSOP16B, -40 to 125 degC Visit Toshiba Electronic Devices & Storage Corporation
    7UL1G07FU Toshiba Electronic Devices & Storage Corporation One-Gate Logic(L-MOS), Non-Inverter Buffer (Open Drain), USV, -40 to 85 degC Visit Toshiba Electronic Devices & Storage Corporation

    LM 4050 IC Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    ic lm 3525

    Abstract: IC LM 3210 lm 4050 ic 4050 spice MC100E122 MC100E122FN MC100E122FNR2 MC10E122 MC10E122FN MC10E122FNR2
    Text: MC10E122, MC100E122 5VĄECL 9ĆBit Buffer The MC10E/100E122 is a 9-bit buffer. The device contains nine non-inverting buffer gates. The 100 Series contains temperature compensation. • 500 ps Max. Propagation Delay • PECL Mode Operating Range: VCC= 4.2 V to 5.7 V


    Original     		PDF MC10E122, MC100E122 MC10E/100E122 EIA/JESD78 AND8003/D MC10E12 r14525 MC10E122/D ic lm 3525 IC LM 3210 lm 4050 ic 4050 spice MC100E122 MC100E122FN MC100E122FNR2 MC10E122 MC10E122FN MC10E122FNR2

    MC100E101

    Abstract: MC100E101FN MC100E101FNR2 MC10E101 MC10E101FN MC10E101FNR2
    Text: MC10E101, MC100E101 5VĄECL Quad 4ĆInput OR/NOR Gate The MC10E/100E101 is a quad 4-input OR/NOR gate. The 100 Series contains temperature compensation. • 500 ps Max. Propagation Delay • PECL Mode Operating Range: VCC= 4.2 V to 5.7 V • http://onsemi.com


    Original     		PDF MC10E101, MC100E101 MC10E/100E101 EIA/JESD78 AND8003/D MC10E101FN r14525 MC10E101/D MC100E101 MC100E101FN MC100E101FNR2 MC10E101 MC10E101FN MC10E101FNR2

    E212 transistor

    Abstract: E112 E212 MC100E112 MC100E112FN MC10E112 MC10E112FN MC10E112FNR2 D200-400
    Text: MC10E112, MC100E112 5VĄECL Quad Driver The MC10E/100E112 is a quad driver with two pairs of OR/NOR outputs from each gate, and a common, buffered enable input. Using the data inputs the device can serve as an ECL memory address fan-out driver. Using just the enable input, the device serves as a clock


    Original     		PDF MC10E112, MC100E112 MC10E/100E112 MC10E/100E111 r14525 MC10E112/D E212 transistor E112 E212 MC100E112 MC100E112FN MC10E112 MC10E112FN MC10E112FNR2 D200-400

    marking CODE D2B

    Abstract: MC100E104 MC100E104FN MC100E104FNR2 MC10E104 MC10E104FN MC10E104FNR2 marking D3B ECL IC NAND
    Text: MC10E104, MC100E104 5VĄECL Quint 2ĆInput AND/NAND Gate The MC10E/100E104 is a quint 2-input AND/NAND gate. The function output F is the OR of all five AND gate outputs, while F is the NOR. The Q outputs need not be terminated if only the F outputs are to be


    Original     		PDF MC10E104, MC100E104 MC10E/100E104 MC10E104FN EIA/JESD78 r14525 MC10E104/D marking CODE D2B MC100E104 MC100E104FN MC100E104FNR2 MC10E104 MC10E104FN MC10E104FNR2 marking D3B ECL IC NAND

    mst 720

    Abstract: MC100E122 MC100E122FN MC100E122FNR2 MC10E122 MC10E122FN MC10E122FNR2
    Text: MC10E122, MC100E122 5VĄECL 9ĆBit Buffer The MC10E/100E122 is a 9-bit buffer. The device contains nine non-inverting buffer gates. The 100 Series contains temperature compensation. • 500 ps Max. Propagation Delay • PECL Mode Operating Range: VCC= 4.2 V to 5.7 V


    Original     		PDF MC10E122, MC100E122 MC10E/100E122 EIA/JESD78 AND8003/D MC10E122FN r14525 MC10E122/D mst 720 MC100E122 MC100E122FN MC100E122FNR2 MC10E122 MC10E122FN MC10E122FNR2

    MC100E104

    Abstract: MC100E104FN MC100E104FNR2 MC10E104 MC10E104FN MC10E104FNR2 ECL IC NAND
    Text: MC10E104, MC100E104 5VĄECL Quint 2ĆInput AND/NAND Gate The MC10E/100E104 is a quint 2-input AND/NAND gate. The function output F is the OR of all five AND gate outputs, while F is the NOR. The Q outputs need not be terminated if only the F outputs are to be


    Original     		PDF MC10E104, MC100E104 MC10E/100E104 MC10E104FN EIA/JESD78 r14525 MC10E104/D MC100E104 MC100E104FN MC100E104FNR2 MC10E104 MC10E104FN MC10E104FNR2 ECL IC NAND

    ic xnor

    Abstract: MC100E107 MC100E107FN MC100E107FNR2 MC10E107 MC10E107FN MC10E107FNR2
    Text: MC10E107, MC100E107 5VĄECL Quint 2ĆInput XOR/XNOR Gate The MC10E/100E107 is a quint 2-input XOR/XNOR gate. The function output F is the OR of all five XOR outputs, while F is the NOR. The Q outputs need not be terminated if only the F outputs are to be used.


    Original     		PDF MC10E107, MC100E107 MC10E/100E107 MC10E107FN EIA/JESD78 r14525 MC10E107/D ic xnor MC100E107 MC100E107FN MC100E107FNR2 MC10E107 MC10E107FN MC10E107FNR2

    ic 4050

    Abstract: marking CODE D2B MC100E101 MC100E101FN MC100E101FNR2 MC10E101 MC10E101FN MC10E101FNR2
    Text: MC10E101, MC100E101 5VĄECL Quad 4ĆInput OR/NOR Gate The MC10E/100E101 is a quad 4-input OR/NOR gate. The 100 Series contains temperature compensation. • 500 ps Max. Propagation Delay • PECL Mode Operating Range: VCC= 4.2 V to 5.7 V • http://onsemi.com


    Original     		PDF MC10E101, MC100E101 MC10E/100E101 EIA/JESD78 AND8003/D MC10E101FN r14525 MC10E101/D ic 4050 marking CODE D2B MC100E101 MC100E101FN MC100E101FNR2 MC10E101 MC10E101FN MC10E101FNR2

    MC100E107

    Abstract: MC100E107FN MC100E107FNR2 MC10E107 MC10E107FN MC10E107FNR2 marking CODE D2B
    Text: MC10E107, MC100E107 5VĄECL Quint 2ĆInput XOR/XNOR Gate The MC10E/100E107 is a quint 2-input XOR/XNOR gate. The function output F is the OR of all five XOR outputs, while F is the NOR. The Q outputs need not be terminated if only the F outputs are to be used.


    Original     		PDF MC10E107, MC100E107 MC10E/100E107 MC10E107FN EIA/JESD78 r14525 MC10E107/D MC100E107 MC100E107FN MC100E107FNR2 MC10E107 MC10E107FN MC10E107FNR2 marking CODE D2B

    E112

    Abstract: E212 MC100E112 MC100E112FN MC10E112 MC10E112FN MC10E112FNR2
    Text: MC10E112, MC100E112 5VĄECL Quad Driver The MC10E/100E112 is a quad driver with two pairs of OR/NOR outputs from each gate, and a common, buffered enable input. Using the data inputs the device can serve as an ECL memory address fan-out driver. Using just the enable input, the device serves as a clock


    Original     		PDF MC10E112, MC100E112 MC10E/100E112 MC10E/100E111 MC10E112FNONlit r14525 MC10E112/D E112 E212 MC100E112 MC100E112FN MC10E112 MC10E112FN MC10E112FNR2

    MC100E116

    Abstract: MC100E116FN MC100E116FNR2 MC10E116 MC10E116FN MC10E116FNR2 E116
    Text: MC10E116, MC100E116 5VĄECL Quint Differential Line Receiver The MC10E/100E116 is a quint differential line receiver with emitter-follower outputs. For applications which require bandwidths greater than that of the E116, the E416 device may be of interest.


    Original     		PDF MC10E116, MC100E116 MC10E/100E116 r14525 MC10E116/D MC100E116 MC100E116FN MC100E116FNR2 MC10E116 MC10E116FN MC10E116FNR2 E116

    MC100E131

    Abstract: MC100E131FN MC100E131FNR2 MC10E131 MC10E131FN MC10E131FNR2
    Text: MC10E131, MC100E131 5VĄECL 4ĆBit D FlipĆFlop The MC10E/100E131 is a quad master-slave D-type flip-flop with differential outputs. Each flip-flop may be clocked separately by holding Common Clock CC LOW and using the Clock Enable (CE) inputs for clocking. Common clocking is achieved by holding the CE


    Original     		PDF MC10E131, MC100E131 MC10E/100E131 r14525 MC10E131/D MC100E131 MC100E131FN MC100E131FNR2 MC10E131 MC10E131FN MC10E131FNR2

    E141

    Abstract: E241 MC100E141 MC100E141FN MC100E141FNR2 MC10E141 MC10E141FN MC10E141FNR2 TRANSISTOR bd 181
    Text: MC10E141, MC100E141 5VĄECL 8ĆBit Shift Register The MC10E/100E141 is an 8-bit full-function shift register. The E141 performs serial/parallel in and serial/parallel out, shifting in either direction. The eight inputs D0 – D7 accept parallel input data, while


    Original     		PDF MC10E141, MC100E141 MC10E/100E141 r14525 MC10E141/D E141 E241 MC100E141 MC100E141FN MC100E141FNR2 MC10E141 MC10E141FN MC10E141FNR2 TRANSISTOR bd 181

    Untitled

    Abstract: No abstract text available
    Text: MC10E116, MC100E116 5VĄECL Quint Differential Line Receiver The MC10E/100E116 is a quint differential line receiver with emitter-follower outputs. For applications which require bandwidths greater than that of the E116, the E416 device may be of interest.


    Original     		PDF MC10E116, MC100E116 MC10E/100E116 r14525 MC10E116/D

    MC100E131

    Abstract: MC100E131FN MC100E131FNR2 MC10E131 MC10E131FN MC10E131FNR2 max5870
    Text: MC10E131, MC100E131 5VĄECL 4ĆBit D FlipĆFlop The MC10E/100E131 is a quad master-slave D-type flip-flop with differential outputs. Each flip-flop may be clocked separately by holding Common Clock CC LOW and using the Clock Enable (CE) inputs for clocking. Common clocking is achieved by holding the CE


    Original     		PDF MC10E131, MC100E131 MC10E/100E131 r14525 MC10E131/D MC100E131 MC100E131FN MC100E131FNR2 MC10E131 MC10E131FN MC10E131FNR2 max5870

    MC100E131FNR2

    Abstract: MC100E131 MC100E131FN MC10E131 MC10E131FN MC10E131FNR2 max5870
    Text: MC10E131, MC100E131 5VĄECL 4ĆBit D FlipĆFlop The MC10E/100E131 is a quad master-slave D-type flip-flop with differential outputs. Each flip-flop may be clocked separately by holding Common Clock CC LOW and using the Clock Enable (CE) inputs for clocking. Common clocking is achieved by holding the CE


    Original     		PDF MC10E131, MC100E131 MC10E/100E131 r14525 MC10E131/D MC100E131FNR2 MC100E131 MC100E131FN MC10E131 MC10E131FN MC10E131FNR2 max5870

    max5870

    Abstract: MC100E131 MC100E131FN MC100E131FNR2 MC10E131 MC10E131FN MC10E131FNR2
    Text: MC10E131, MC100E131 5VĄECL 4ĆBit D FlipĆFlop The MC10E/100E131 is a quad master-slave D-type flip-flop with differential outputs. Each flip-flop may be clocked separately by holding Common Clock CC LOW and using the Clock Enable (CE) inputs for clocking. Common clocking is achieved by holding the CE


    Original     		PDF MC10E131, MC100E131 MC10E/100E131 r14525 MC10E131/D max5870 MC100E131 MC100E131FN MC100E131FNR2 MC10E131 MC10E131FN MC10E131FNR2

    Untitled

    Abstract: No abstract text available
    Text: MC10E116, MC100E116 5VĄECL Quint Differential Line Receiver The MC10E/100E116 is a quint differential line receiver with emitter-follower outputs. For applications which require bandwidths greater than that of the E116, the E416 device may be of interest.


    Original     		PDF MC10E116, MC100E116 MC10E/100E116 r14525 MC10E116/D

    E141

    Abstract: E241 MC100E141 MC100E141FN MC100E141FNR2 MC10E141 MC10E141FN MC10E141FNR2
    Text: MC10E141, MC100E141 5VĄECL 8ĆBit Shift Register The MC10E/100E141 is an 8-bit full-function shift register. The E141 performs serial/parallel in and serial/parallel out, shifting in either direction. The eight inputs D0 – D7 accept parallel input data, while


    Original     		PDF MC10E141, MC100E141 MC10E/100E141 r14525 MC10E141/D E141 E241 MC100E141 MC100E141FN MC100E141FNR2 MC10E141 MC10E141FN MC10E141FNR2

    MC100E457

    Abstract: MC100E457FN MC100E457FNR2 MC10E457 MC10E457FN MC10E457FNR2 marking CODE D2B
    Text: MC10E457, MC100E457 5VĄECL Triple Differential 2:1 Multiplexer The MC10E457/100E457 is a 3-bit differential 2:1 multiplexer. The fully differential data path makes the device ideal for multiplexing low skew clock or other skew sensitive signals. The higher frequency outputs provide the device with a > 1.0 GHz


    Original     		PDF MC10E457, MC100E457 MC10E457/100E457 r14525 MC10E457/D MC100E457 MC100E457FN MC100E457FNR2 MC10E457 MC10E457FN MC10E457FNR2 marking CODE D2B

    Untitled

    Abstract: No abstract text available
    Text: MC10E452, MC100E452 5VĄECL 5ĆBit Differential Register The MC10E/100E452 is a 5-bit differential register with differential data inputs and outputs and clock. The registers are triggered by a positive transition of the positive clock (CLK) input. A high on the


    Original     		PDF MC10E452, MC100E452 MC10E/100E452 r14525 MC10E452/D

    MC100E457FN

    Abstract: MC100E457FNR2 MC10E457 MC10E457FN MC10E457FNR2 MC100E457
    Text: MC10E457, MC100E457 5VĄECL Triple Differential 2:1 Multiplexer The MC10E457/100E457 is a 3-bit differential 2:1 multiplexer. The fully differential data path makes the device ideal for multiplexing low skew clock or other skew sensitive signals. The higher frequency outputs provide the device with a > 1.0 GHz


    Original     		PDF MC10E457, MC100E457 MC10E457/100E457 r14525 MC10E457/D MC100E457FN MC100E457FNR2 MC10E457 MC10E457FN MC10E457FNR2 MC100E457

    MC100E452

    Abstract: MC100E452FN MC100E452FNR2 MC10E452 MC10E452FN MC10E452FNR2 DSA001316
    Text: MC10E452, MC100E452 5VĄECL 5ĆBit Differential Register The MC10E/100E452 is a 5-bit differential register with differential data inputs and outputs and clock. The registers are triggered by a positive transition of the positive clock (CLK) input. A high on the


    Original     		PDF MC10E452, MC100E452 MC10E/100E452 r14525 MC10E452/D MC100E452 MC100E452FN MC100E452FNR2 MC10E452 MC10E452FN MC10E452FNR2 DSA001316

    mr 4020 pin assignment

    Abstract: E137 MC100E137 MC100E137FN MC100E137FNR2 MC10E137 MC10E137FN MC10E137FNR2 LM 4800 100E137
    Text: MC10E137, MC100E137 5VĄECL 8ĆBit Ripple Counter The MC10E/100E137 is a very high speed binary ripple counter. The two least significant bits were designed with very fast edge rates while the more significant bits maintain standard ECLinPSt output edge rates. This allows the counter to operate at very high frequencies while


    Original     		PDF MC10E137, MC100E137 MC10E/100E137 r14525 MC10E137/D mr 4020 pin assignment E137 MC100E137 MC100E137FN MC100E137FNR2 MC10E137 MC10E137FN MC10E137FNR2 LM 4800 100E137