Untitled
Abstract: No abstract text available
Text: LH5P8512 FEATURES • 5 2 4 ,2 8 8 x 8 bit organization • Access time: 60 /7 0 /8 0 ns M AX. • Cycle time: 110/130/150 ns (M IN .) PRELIMINARY CMOS 4M (512K • x 8) Pseudo-Static RAM Compatible with J E D E C standard 4M S RA M pinout • Packages:
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LH5P8512
32-pin,
600-m
525-m
400-m
LH5P8512
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Sharp IIS
Abstract: C31A SHARP ORDERING INFORMATION
Text: SHARP b lE CORP LH5P8512 FEATURES • 524,288 x 8 bit organization • Access time: 60/70/80 ns MAX. • Cycle time: 110/130/150 ns (MIN.) • Power supply: D • ûlfiOTSfi GG G T b 5 5 D3S H S R P J PRELIMINARY CMOS 4M (512K x 8) Pseudo-Static RAM •
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OCR Scan
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PDF
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LH5P8512
32-pin,
600-mil
525-mil
400-mil
LH5P8512
Sharp IIS
C31A
SHARP ORDERING INFORMATION
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Untitled
Abstract: No abstract text available
Text: LH5P8512 FEATURES PRELIMINARY CM OS 4M 512K x 8 Pseudo-Static RAM • • 5 24,28 8 x 8 bit organization • Access time: 60 /7 0 /8 0 ns (M AX.) • Cycle time: 110/130/150 ns (M IN .) • Power supply: Compatible with JE D E C standard 4M SRAM pinout •
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OCR Scan
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PDF
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LH5P8512
32-pin,
600-m
525-m
400-m
LH5P8512
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LH64256BK70
Abstract: Lh64256bk-70
Text: MEMORIES ★Under development • Pseudo S tatic RAMs Gipäfifty rüm ^H M o n Modal No. worfexblta t LH5P832/D/N-10 256k Supply.currant AOOMtttM# Cyetotime operating/standby (na)MAX. (na) MIN. 100 160 (mA) MAX. Supply voltage M Control signal« 65/3 32k x 8
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LH5P832/D/N-10
28DIP/
28SK-DIP/
28SOP
32DIP/32SOP
32SOP
40DIP/40SOP
LH5P832/D/N-12
LH5P860/N-80
LH5P864N-80
LH64256BK70
Lh64256bk-70
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lh57257
Abstract: IR2E31 IR2E01 IR2C07 IR2E27 IR2E24 IR2E19 IR2E31A IR3n06 IR2E02
Text: Index Model No. ARM7D CPU Core Bi-CMOS 1 27 40,42 _ _ CMOS CMOS CMOS CMOS CMOS 4A 5A 8 A AH D ID1 Series ID2 Series 40,42 40.42 40,42 40,42 40 B ü.’1*"! 14,15 14 m IR2339 IR2403 IR2406 IR2406G IR2410 IR2411 IR2415 IR2419 IR2420 IR2422 IR2425 IR2429
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IR2E201
IR2E24
IR2E27/A
IR2E28
IR2E29
IR2E30
IR2E31/A
IR2E32N9
IR2E34
IR2E41
lh57257
IR2E31
IR2E01
IR2C07
IR2E27
IR2E19
IR2E31A
IR3n06
IR2E02
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Cross Reference
Abstract: Pseudostatic RAM TC51832
Text: Pseudo-Static RAM Cross Reference PSEUDO-STATIC RAM CROSS REFERENCE ORGANIZATIONAL STRUCTURE 32K 64K 128K X X X 8 8 8 128K x 8 w/CS 512K 2-50 X 8 SHARP MODEL LH5P832 LH5P864 LH5P8128 COMPETITIVE VENDOR COMPETITIVE MODEL ACCESS TIME PACKAGE OPTIONS Hitachi
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LH5P832
HM65256B
TC51832
LH5P864
HM658128A
TC518128A
TC518129A
HM658512
TC518512
LH5P8128
Cross Reference
Pseudostatic RAM
TC51832
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sp8512
Abstract: No abstract text available
Text: PRELIMINARY L H 5 P 8 5 1 2 FEATURES • 5 2 4 ,2 8 8 x 8 bit organization • Access time: 6 0 /7 0 /8 0 ns M AX. • Cycle time: 110/130/150 ns (M IN .) • Power supply: CMOS 4M (512K • x 8) Pseudo-Static RAM Compatible with J E D E C standard 4M SRA M pinout
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OCR Scan
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PDF
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32-pin,
600-m
525-m
400-m
LH5P8512
LH5P8512
600-mil
sp8512
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256k x 4
Abstract: No abstract text available
Text: MEMORIES ★Under development Capacity Configuration Model No. Access time ns 60 256k 32k x 8 70 Package SK BO 100 120 150 DIP SOP TSOP DIP LH5P832 — 28 28 LH5P860 n 28 32 64k x 8 LH5P864 — 32 512k Pseudo static RAM 32k x 16 LH5P1632 I- — 40 40 LH5P8128
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LH5P832
LH5P860
LH5P864
LH5P1632
LH5P8128
LH5P8129
LH5P8512
LH21256
LH64256B
256k x 4
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