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    QuickLogic Corporation QL24X32B-2PF144C

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    L16X2

    Abstract: ic logic gates
    Text: pASIC 1 FAMILY ViaLink Technology Very-High-Speed CMOS FPGAs gj V ery H igh S p eed - V iaL ink m etal-to-m etal, program m able-via an ti­ fuse technology ensures useful internal logic function speeds at over 100 M H z, and logic cell delays o f under 2 ns.


    OCR Scan     		14-input L16X2 ic logic gates PDF

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    Abstract: No abstract text available
    Text: L24x32B WildCat 8000 Very-High-Speed 8K 24K Gate CMOS FPGA ADVANCE DATA pASIC HIGHLIGHTS Cl Very High Speed - ViaLink metal-to-metal program m able-via anti­ fuse technology, allows counter speeds over 150 M Hz and logic cell delays of under 2 ns. B High Usable Density - A 24-by-32 array o f768 logic cells provides 24,000


    OCR Scan     		QL24x32B 24-by-32 100and 144-pin 225-pin 16-bit 100-pin L24x32B 100-144-pin 16x24B PDF

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    Abstract: No abstract text available
    Text: L24X32BL WildCaX 8000L Low Power 3.3 Volt Operation, 8K Gate FPGA P 5V Tolerant I/Os - Support interface to 5 V o lt C M O S , N M O S and bipolar devices by sinking up to 12 m A see IIH specification . .8000 usable gates, 180 I/O pins Q| High Usable Density - A 24-by-32 array o f768 logic cells provides 24,000


    OCR Scan     		QL24X32BL 8000L 24-by-32 144pin 208-pin 24x32BL PQ208 PF144 144-pin PQ208 PDF