Please enter a valid full or partial manufacturer part number with a minimum of 3 letters or numbers

    JSCC FORM Search Results

    JSCC FORM Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    TLP3406SRH4 Toshiba Electronic Devices & Storage Corporation Photorelay (MOSFET output, 1-form-a), 30 V/0.9 A, 300 Vrms, S-VSON16T Visit Toshiba Electronic Devices & Storage Corporation
    TLP3407SRA Toshiba Electronic Devices & Storage Corporation Photorelay (MOSFET output, 1-form-a), 60 V/1 A, 500 Vrms, S-VSON4T Visit Toshiba Electronic Devices & Storage Corporation
    TLP3407SRH Toshiba Electronic Devices & Storage Corporation Photorelay (MOSFET output, 1-form-a), 60 V/1 A, 500 Vrms, S-VSON4T Visit Toshiba Electronic Devices & Storage Corporation
    TLP3412SRHA4 Toshiba Electronic Devices & Storage Corporation Photorelay (MOSFET output, 1-form-a), 60 V/0.25 A, 300 Vrms, S-VSON16T Visit Toshiba Electronic Devices & Storage Corporation
    TLP241B Toshiba Electronic Devices & Storage Corporation Photorelay (MOSFET output, 1-form-a), 100 V/2.0 A, 5000 Vrms, DIP4 Visit Toshiba Electronic Devices & Storage Corporation

    JSCC FORM Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    DSP56k instruction

    Abstract: ASR16 DSP56K dsp56001
    Text: APPENDIX A INSTRUCTION SET DETAILS • Arithmetic MAC su,uu • Bit Field Manipulation • Program Control ABS NEG ADC NEGC ADD NORM ASL RND ASL4 SBC ASR SUB ASR4 SUBL ASR16 SWAP Tcc DOLoop Jcc CLR TFR DO FOREVER JMP CLR24 TFR2 JSR CMP ENDDO TST JScc CMPM


    Original     		PDF ASR16 CLR24 DEC24 INC24 DSP56k instruction ASR16 DSP56K dsp56001

    A-18

    Abstract: DSP56001 DSP56K Jscc form
    Text: INSTRUCTION DESCRIPTIONS DIV Operation: DIV Divide Interation If D[55]⊕S[23]=1, 55 47 23 then C+S D C–S D Destination Accumulator D 55 47 23 else Destination Accumulator D where ⊕ denotes the logical exclusive OR operator Assembler Syntax: DIV S,D Description:


    Original     		PDF 48-bit 56-bits 56-bit 24-bit A-18 DSP56001 DSP56K Jscc form

    A244D

    Abstract: A-18 A659 a244
    Text: Instruction Formats and opcodes: 23 16 15 EOR S,D 8 DATA BUS MOVE FIELD 7 1 J J d 1 1 OPTIONAL EFFECTIVE ADDRESS EXTENSION 23 EOR #xx,D 16 15 23 EOR #xxxxxx,D 1 1 i i i i i 16 15 1 1 8 7 i 1 8 7 1 d 1 1 1 d 1 1 IMMEDIATE DATA EXTENSION Instruction Fields:


    Original     		PDF

    DO-15X

    Abstract: No abstract text available
    Text: Freescale Semiconductor, Inc. BRKcc BRKcc Exit Current DO Loop Conditionally Example: DO Y0,END_LP : LC,A Y1,A Freescale Semiconductor, Inc. MOVEC CMP BRKNE ;exec. loop ending at END_LP Y0 times ;get current value of loop counter (LC) ;compare loop counter with value in Y1


    Original     		PDF

    Untitled

    Abstract: No abstract text available
    Text: BRKcc BRKcc Exit Current DO Loop Conditionally Example: DO Y0,END_LP : LC,A Y1,A MOVEC CMP BRKNE ;exec. loop ending at END_LP Y0 times ;get current value of loop counter (LC) ;compare loop counter with value in Y1 ;go to first instruction after Do loop if LC not equal to Y1


    Original     		PDF 16-bit

    pipeline in core i3

    Abstract: DSP56300 bscc core i3 addressing modes
    Text: Appendix B INSTRUCTION EXECUTION TIMING B-1 INTRODUCTION This section describes the various aspects of execution timing analysis for each instruction mnemonic and for various instruction sequences. The section consists of the following tables and information:


    Original     		PDF DSP56300 pipeline in core i3 bscc core i3 addressing modes

    DSP56K

    Abstract: A-18
    Text: INSTRUCTION TIMING A.8 INSTRUCTION TIMING This section describes how to calculate DSP56K instruction timing manually using the tables provided. Three complete examples illustrate the “layered’’ nature of the tables. Alternatively, the user can determine the number of instruction program words and the


    Original     		PDF DSP56K DSP56K A-18

    DSP56000

    Abstract: DSP56001
    Text: A.7 INSTRUCTION TIMING This section describes how one can calculate DSP56000/DSP56001 instruction timing manually using the tables provided in this section. Three complete examples are presented to illustrate the ‘‘layered’’ nature of the tables. Alternatively, the user can obtain the number of


    Original     		PDF DSP56000/DSP56001 DSP56000 DSP56001

    DSP56001 users manual

    Abstract: DSP56000 DSP56001 bus ssl
    Text: Freescale Semiconductor, Inc. A.7 INSTRUCTION TIMING Freescale Semiconductor, Inc. This section describes how one can calculate DSP56000/DSP56001 instruction timing manually using the tables provided in this section. Three complete examples are presented to


    Original     		PDF DSP56000/DSP56001 DSP56001 users manual DSP56000 DSP56001 bus ssl

    DSP56000

    Abstract: DSP56001
    Text: APPENDIX A INSTRUCTION SET DETAILS This appendix contains detailed information about each instruction in the DSP56000/ DSP56001 instruction set. An instruction guide is presented first to help understand the individual instruction descriptions. This guide is followed by sections on notation and


    Original     		PDF DSP56000/ DSP56001 DSP56000/DSP56001 DSP56000

    DSP56001

    Abstract: 56001 DSP56001 users manual DSP56000 000E-6
    Text: Freescale Semiconductor, Inc. APPENDIX A INSTRUCTION SET DETAILS Freescale Semiconductor, Inc. This appendix contains detailed information about each instruction in the DSP56000/ DSP56001 instruction set. An instruction guide is presented first to help understand the


    Original     		PDF DSP56000/ DSP56001 DSP56000/DSP56001 56001 DSP56001 users manual DSP56000 000E-6

    001C

    Abstract: DSP56100
    Text: SECTION 7 PROCESSING STATES STOP NORMAL WAIT RESET EXCEPTION MOTOROLA PROCESSING STATES 7-1 SECTION CONTENTS 7.1 7.2 7.2.1 7.2.2 7.2.2.1 7.2.2.2 7.2.2.3 7.2.2.4 7.2.2.5 7.2.2.6 7.2.2.7 7.3 7.3.1 7.3.2 7.3.3 7.3.4 7.3.4.1 7.3.4.2 7.3.4.3 7.3.5 7.3.5.1 7.3.5.2


    Original     		PDF

    001C

    Abstract: DSP56100
    Text: Freescale Semiconductor, Inc. SECTION 7 Freescale Semiconductor, Inc. PROCESSING STATES STOP NORMAL WAIT RESET EXCEPTION MOTOROLA PROCESSING STATES For More Information On This Product, Go to: www.freescale.com 7-1 Freescale Semiconductor, Inc. Freescale Semiconductor, Inc.


    Original     		PDF

    DSP96002

    Abstract: Floating-Point Arithmetic floating point adder
    Text: SECTION 6 INSTRUCTION SET AND EXECUTION 6.1 INTRODUCTION This chapter introduces the DSP96002 instruction set and instruction format. The complete range of instruction capabilities combined with the flexible addressing modes described in Chapter 5 provide a very


    Original     		PDF DSP96002 DSP96002, Floating-Point Arithmetic floating point adder

    cpcap 3.2

    Abstract: cpcap 3.2 ESD DDR3 timing micron ddr3 DSP56300 DSP56309 cpcap motorola 0J17D
    Text: MOTOROLA Semiconductor Products Sector Engineering Bulletin Functional Differences Between Masks 5H80G and 0J17D of the DSP56309 This document describes the differences between masks of the DSP56309: the new mask, 0J17D, and the mask immediately preceding it, 5H80G. The new 0J17D mask of the DSP56309 uses


    Original     		PDF 5H80G 0J17D DSP56309 DSP56309: 0J17D, 5H80G. DSP56309 0J17D EB343/D: cpcap 3.2 cpcap 3.2 ESD DDR3 timing micron ddr3 DSP56300 cpcap motorola

    cpcap 3.2 ESD

    Abstract: ES79 cpcap motorola
    Text: MOTOROLA Rev. 1 , 11/99 Semiconductor Technical Bulletin Functional Differences Between Masks 5H80G and 0J17D of the DSP56309 This document describes the differences between masks of the DSP56309: the new mask, 0J17D, and the mask immediately preceding it, 5H80G. The new 0J17D mask of


    Original     		PDF 5H80G 0J17D DSP56309 DSP56309: 0J17D, 5H80G. DSP56309 DSP56300 cpcap 3.2 ESD ES79 cpcap motorola

    ASR16

    Abstract: DSP56100 bscc
    Text: Freescale Semiconductor, Inc. APPENDIX A Freescale Semiconductor, Inc. PRELIMINARY DSP56100 FAMILY INSTRUCTION SET • Arithmetic MAC su,uu • Bit Field Manipulation • Program Control ABS NEG ADC NEGC ADD NORM ASL RND ASL4 SBC ASR SUB ASR4 SUBL ASR16


    Original     		PDF DSP56100 ASR16 CLR24 DEC24 ASR16 bscc

    DSP56300

    Abstract: DSP56309 EB343
    Text: Freescale Semiconductor Engineering Bulletin EB343 Rev. 3, 10/2005 Functional Differences Between Masks 5H80G and 0J17D of the DSP56309 This document describes the differences between masks of the DSP56309: the 0J17D and the mask immediately preceding it,


    Original     		PDF EB343 5H80G 0J17D DSP56309 DSP56309: 5H80G. DSP56309 DSP56300 EB343

    OMR H

    Abstract: Weighing scale circuit "saturation arithmetic"
    Text: INDEX —A— A Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 Aborted Instructions . . . . . . . . . . . . . . . . . . . . 7-25 ABS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .A-22 Absolute Address . . . . . . . . . . . . . . . . . . . . . . 6-14


    Original     		PDF

    DSP56300

    Abstract: DSP56303
    Text: MOTOROLA Semiconductor Products Sector Engineering Bulletin Functional Differences Between Masks 4J22A and 0K36A of the DSP56303 This document describes the differences between masks of the DSP56303: the new mask, 0K36A, and the mask immediately preceding it, 4J22A. The new 0K36A mask of the DSP56303 uses


    Original     		PDF 4J22A 0K36A DSP56303 DSP56303: 0K36A, 4J22A. DSP56303 0K36A EB340/D: DSP56300

    DSP56300

    Abstract: DSP56303 EB340 SP 9442
    Text: Freescale Semiconductor Engineering Bulletin EB340 Rev. 3, 2/2006 Functional Differences Between Masks 4J22A and 0K36A of the DSP56303 This document describes the differences between masks of the DSP56303: the new mask, 0K36A, and the mask immediately preceding it, 4J22A. The new 0K36A mask of


    Original     		PDF EB340 4J22A 0K36A DSP56303 DSP56303: 0K36A, 4J22A. DSP56303 DSP56300 EB340 SP 9442

    ASR16

    Abstract: No abstract text available
    Text: Freescale Semiconductor, Inc. Freescale Semiconductor, Inc. SECTION 6 INSTRUCTION SET AND EXECUTION Fetch F1 Decode Execute Instruction Cycle: 1 MOTOROLA F2 D1 F3 D2 E1 F3e D3 E2 F4 F5 F6 D3e D4 D5 E3 E3e E4 … … … 2 3 4 5 … 6 7 INSTRUCTION SET AND EXECUTION


    Original     		PDF

    Untitled

    Abstract: No abstract text available
    Text: SECTION 6 INSTRUCTION SET AND EXECUTION Fetch F1 Decode Execute Instruction Cycle: 1 MOTOROLA F2 D1 F3 D2 E1 F3e D3 E2 F4 F5 F6 D3e D4 D5 E3 E3e E4 … … … 2 3 4 5 … 6 7 INSTRUCTION SET AND EXECUTION 6-1 SECTION CONTENTS 6.1 6.2 6.2.1 6.2.2 6.2.3 6.2.4


    Original     		PDF

    Untitled

    Abstract: No abstract text available
    Text: Wfipl H EW LETT mLftm P A C K A R D Single Chip LED Light Bar Technical Data HLMP-T200 HLMP-T300 HLMP-T400 HLMP-T500 Features • Flat Rectangular Light Emitting Surface • Choice of 4 Bright Colors • Excellent On/Off Contrast • Ideal as Flush Mounted


    OCR Scan     		PDF HLMP-T200 HLMP-T300 HLMP-T400 HLMP-T500 HLMP-T200/-T300/-T400/ -T500