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    JEDEC CP 28 Search Results

    JEDEC CP 28 Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    TMP139AIYAHR Texas Instruments JEDEC DDR5 temperature sensor with 0.5 °C accuracy 6-DSBGA -40 to 125 Visit Texas Instruments Buy
    SN74SSQEA32882ZALR Texas Instruments JEDEC SSTE32882 Compliant 28-Bit to 56-Bit Registered Buffer with Address-Parity Test 176-NFBGA 0 to 85 Visit Texas Instruments Buy
    SN74SSQE32882ZALR Texas Instruments JEDEC SSTE32882 Compliant 28-Bit to 56-Bit Registered Buffer with Address-Parity Test 176-NFBGA 0 to 85 Visit Texas Instruments
    SN74SSQEB32882ZALR Texas Instruments JEDEC SSTE32882 Compliant 28-Bit to 56-Bit Registered Buffer with Address-Parity Test 176-NFBGA 0 to 85 Visit Texas Instruments Buy
    SN74SSQEC32882ZALR Texas Instruments JEDEC SSTE32882 Compliant Low Power 28-Bit to 56-Bit Registered Buffer with Address-Parity Test 176-NFBGA 0 to 85 Visit Texas Instruments Buy

    JEDEC CP 28 Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    4000B

    Abstract: 74HC4024 74HC4024D 74HC4024DB 74HC4024N 74HC4024PW
    Text: 74HC4024 7-stage binary ripple counter Product data sheet 1. General description The 74HC4024 is a high-speed Si-gate CMOS device and is pin compatible with the 4024 of the 4000B series. The 74HC4024 is specified in compliance with JEDEC standard no. 7A. The 74HC4024 is a 7-stage binary ripple counter with a clock input CP , an overriding


    Original     		PDF 74HC4024 74HC4024 4000B OT108-1 076E06 MS-012 74HC4024D 74HC4024DB 74HC4024N 74HC4024PW

    74LVC377

    Abstract: No abstract text available
    Text: INTEGRATED CIRCUITS DATA SHEET 74LVC377 Octal D-type flip-flop with data enable; positive-edge trigger Product specification Supersedes data of 1998 Jul 29 2004 May 28 Philips Semiconductors Product specification Octal D-type flip-flop with data enable; positive-edge trigger


    Original     		PDF 74LVC377 JESD8B/JESD36 EIA/JESD22-A114-B EIA/JESD22-A115-A SCA76 R20/04/pp16

    Untitled

    Abstract: No abstract text available
    Text: 74LVC2G74 Single D-type flip-flop with set and reset; positive edge trigger Rev. 8 — 28 November 2011 Product data sheet 1. General description The 74LVC2G74 is a single positive-edge triggered D-type flip-flop with individual data D inputs, clock (CP) inputs, set (SD) and reset (RD) inputs, and complementary Q and Q


    Original     		PDF 74LVC2G74 74LVC2G74

    Untitled

    Abstract: No abstract text available
    Text: 74AUP1G79 Low-power D-type flip-flop; positive-edge trigger Rev. 6 — 28 June 2012 Product data sheet 1. General description The 74AUP1G79 provides the single positive-edge triggered D-type flip-flop. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock


    Original     		PDF 74AUP1G79 74AUP1G79

    Untitled

    Abstract: No abstract text available
    Text: 74AUP1G79 Low-power D-type flip-flop; positive-edge trigger Rev. 5 — 28 November 2011 Product data sheet 1. General description The 74AUP1G79 provides the single positive-edge triggered D-type flip-flop. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock


    Original     		PDF 74AUP1G79 74AUP1G79

    74LVC1G80

    Abstract: 74LVC1G80GF 74LVC1G80GM 74LVC1G80GV 74LVC1G80GW
    Text: 74LVC1G80 Single D-type flip-flop; positive-edge trigger Rev. 9 — 28 September 2010 Product data sheet 1. General description The 74LVC1G80 provides a single positive-edge triggered D-type flip-flop. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition


    Original     		PDF 74LVC1G80 74LVC1G80 74LVC1G80GF 74LVC1G80GM 74LVC1G80GV 74LVC1G80GW

    74hc374an

    Abstract: VHC374 74VHC374MTC 74VHC374SJ M20D MS-013 MTC20 74HC374 74VHC374 74VHC374M
    Text: 74VHC374 Octal D-Type Flip-Flop with 3-STATE Outputs tm Features General Description • High Speed: tPD = 5.4ns typ at VCC = 5V ■ High noise immunity: VNIH = VNIL = 28% VCC (Min.) The VHC374 is an advanced high speed CMOS octal flip-flop with 3-STATE output fabricated with silicon gate


    Original     		PDF 74VHC374 VHC374 74VHC374 74hc374an 74VHC374MTC 74VHC374SJ M20D MS-013 MTC20 74HC374 74VHC374M

    Untitled

    Abstract: No abstract text available
    Text: 74AUP1G80 Low-power D-type flip-flop; positive-edge trigger Rev. 4 — 28 June 2012 Product data sheet 1. General description The 74AUP1G80 provides the single positive-edge triggered D-type flip-flop. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock


    Original     		PDF 74AUP1G80 74AUP1G80

    Untitled

    Abstract: No abstract text available
    Text: 74VHC374 Octal D-Type Flip-Flop with 3-STATE Outputs tm Features General Description • High Speed: tPD = 5.4ns typ at VCC = 5V ■ High noise immunity: VNIH = VNIL = 28% VCC (Min.) The VHC374 is an advanced high speed CMOS octal flip-flop with 3-STATE output fabricated with silicon gate


    Original     		PDF 74VHC374 VHC374 74VHC374

    74HC299

    Abstract: 74HC299D 74HC299DB 74HC299N 74HC299PW 74HCT299 74HCT299D 74HCT299DB JESD22-A114E
    Text: 74HC299; 74HCT299 8-bit universal shift register; 3-state Rev. 03 — 28 July 2008 Product data sheet 1. General description The 74HC299; 74HCT299 are high-speed Si-gate CMOS devices which are pin-compatible with Low-power Schottky TTL LSTTL devices. They are specified in


    Original     		PDF 74HC299; 74HCT299 74HCT299 HCT299 74HC299 74HC299D 74HC299DB 74HC299N 74HC299PW 74HCT299D 74HCT299DB JESD22-A114E

    Untitled

    Abstract: No abstract text available
    Text: 74HC299; 74HCT299 8-bit universal shift register; 3-state Rev. 03 — 28 July 2008 Product data sheet 1. General description The 74HC299; 74HCT299 are high-speed Si-gate CMOS devices which are pin-compatible with Low-power Schottky TTL LSTTL devices. They are specified in


    Original     		PDF 74HC299; 74HCT299 74HCT299 HCT299

    74HC-HCT4094

    Abstract: 74hct4094d 74HC4094D 74hct4094 CP/2012
    Text: 74HC4094; 74HCT4094 8-stage shift-and-store bus register Rev. 5 — 28 June 2012 Product data sheet 1. General description The 74HC4094; 74HCT4094 are high-speed Si-gate CMOS devices and are pin compatible with the 4094 of the 4000B series. It is specified in compliance with JEDEC


    Original     		PDF 74HC4094; 74HCT4094 74HCT4094 4000B HCT4094 74HC-HCT4094 74hct4094d 74HC4094D CP/2012

    Untitled

    Abstract: No abstract text available
    Text: 74HC4094; 74HCT4094 8-stage shift-and-store bus register Rev. 5 — 28 June 2012 Product data sheet 1. General description The 74HC4094; 74HCT4094 are high-speed Si-gate CMOS devices and are pin compatible with the 4094 of the 4000B series. It is specified in compliance with JEDEC


    Original     		PDF 74HC4094; 74HCT4094 74HCT4094 4000B HCT4094

    HEF4094BP

    Abstract: HEF4094B HEF4094BT HEF4094BTS SSOP16
    Text: HEF4094B 8-stage shift-and-store bus register Rev. 05 — 28 July 2009 Product data sheet 1. General description The HEF4094B is an 8-stage serial shift register. It has a storage latch associated with each stage for strobing data from the serial input to parallel buffered 3-state outputs


    Original     		PDF HEF4094B HEF4094B HEF4094BP HEF4094BT HEF4094BTS SSOP16

    E 9547

    Abstract: digital countdown timer xtr 101 74F525 74F525PC 74F525QC 74F525SC C1995 F525 M28B
    Text: 74F525 Programmable Counter General Description Features The ’F525 is a multi-function 28-pin device It consists of a 16-bit count-down counter logic to control the counter logic to control the state of the outputs and a PLA to decode the particular function selected by the user The list of highspeed timing applications include


    Original     		PDF 74F525 28-pin 16-bit 74F525QC 28-Lead 74F52m E 9547 digital countdown timer xtr 101 74F525 74F525PC 74F525QC 74F525SC C1995 F525 M28B

    JEDEC Code

    Abstract: JEDEC max1918 package outline weight EIAJ 133-AA JEDEC CP 28 MO133A
    Text: Package Outline Dimensions 24 16.90 17.27 Max 19 18 î n r - in 13 n n n r - ii- in 6 7 0.74 12 Hitachi code JEDEC code EIAJ code Weight g CP-24DB MO-077AA SC-632-A 0.80 9.40 ± 0.25 Hitachi code JEDEC code EIAJ code Weight (g) CP-28DA MO-061 AA SC-637-B


    OCR Scan     		PDF CP-24DB MO-077AA SC-632-A CP-28DA MO-061 SC-637-B CP-42D TTP-28DA MO-133AA TTP-44DE JEDEC Code JEDEC max1918 package outline weight EIAJ 133-AA JEDEC CP 28 MO133A

    Am29C82

    Abstract: No abstract text available
    Text: Am29C821 / Am29C823 Am29C921 /Am29C923 High-Performance CMOS Bus Interface Registers High-speed parallel positive edge-triggered registers with D-type flip-flops - CP-Y propagation delay = 8 ns typical • Low standby power • JEDEC FCT-compatible specs •


    OCR Scan     		PDF Am29C821 Am29C823 Am29C921 /Am29C923 /Am29C823 Am29C921/Am29C923 10-bit) Am29C900 Am29C82

    Am29CB21

    Abstract: am29c800 cis 11-pin Am29C821
    Text: Am29C821 / Am29C823 Am29C921 / Am29C923 High-Performance CMOS Bus Interface Registers • • • High-speed parallel positive edge-triggered registers with D-type flip-flops - CP-Y propagation delay - 8 ns typical Low standby power JEDEC FCT-compatible specs


    OCR Scan     		PDF Am29C821 Am29C823 Am29C921 Am29C923 Am29C821/ Am29C921/ 10-bit) Am29C900 Am29CB21 am29c800 cis 11-pin

    amd am2 pinout

    Abstract: AM29C821/B3A pinout AM2 AMD CD3024 PD3024 AM29C823 AM29C821PC
    Text: Am29C821 / Am29C823 Am29C921 /Am29C923 High-Performance CMOS Bus Interface Registers High-speed parallel positive edge-triggered registers with D-type flip-flops - CP-Y propagation delay = 8 ns typical • Low standby power • JEDEC FCT-compatible specs •


    OCR Scan     		PDF Am29C821 Am29C823 Am29C921 Am29C923 10-bit) Am29C900 AIS-WCP-20M-01/88-0 amd am2 pinout AM29C821/B3A pinout AM2 AMD CD3024 PD3024 AM29C821PC

    CD3024

    Abstract: PD3024 AM29C821PC
    Text: Am29C821 / Am29C823 Am29C921 /Am29C923 High-Performance C M O S Bus Interface Registers High-speed parallel positive edge-triggered registers with D-type flip-flops - CP-Y propagation delay = 8 ns typical • Low standby power • JEDEC FCT-compatible specs


    OCR Scan     		PDF Am29C821/Am29C823 Am29C921 Am29C923 10-bit) Am29C900 Am29C821 Am29C823 Am29C800 CS-11 AIS-WCP-20M-01/88-0 CD3024 PD3024 AM29C821PC

    Untitled

    Abstract: No abstract text available
    Text: cP ÏITSU May 1997 Revision 1.0 SDC4UV7282C- 67/84/100/125 T-S 32MByte (4M x 72) CMOS Synchronous DRAM Module - ECC General Description The SDC4UV7282C-(67/84/100/125)T-S is a high performance, 32-megabtye synchronous, dynamic RAM module organized as 4M words by 72 bits, in a 168-pin, JEDEC ECC configuration, dual-in-line memory module (DIMM) package.


    OCR Scan     		PDF SDC4UV7282C- 32MByte 32-megabtye 168-pin, MB81117822A- 374175b

    54LS393

    Abstract: No abstract text available
    Text: Signetics 54LS393 Counter Dual 4-Bit Binary Ripple Counter Product Specification Military Logic Products FEATURES • Two 4-bit binary counters • Divide-by any binary module up to 28 in one package • Two Master Resets to clear each 4-bit counter individually


    OCR Scan     		PDF 54LS393 54LS393 54LSXXX 500ns 515ns 1N916 1N3064,

    823T

    Abstract: 825T
    Text: QSFCT821T, 823T, 825T, 2821T, 2823T, 2825T Ö High Speed CMOS Bus Interface 8-, 9-, and 10-Bit Registers QS54/74FCT821T QS54/74FCT823T QS54/74F CT825T QS54/74FCT2821T QS54/74FCT2823T QS54/74FCT2825T FEATURES/BENEFITS • Pin and function compatible to the 74F821/3/5


    OCR Scan     		PDF QSFCT821T, 2821T, 2823T, 2825T 10-Bit QS54/74FCT821T QS54/74FCT823T QS54/74FCT825T QS54/74FCT2821T QS54/74FCT2823T 823T 825T

    Untitled

    Abstract: No abstract text available
    Text: IM P \ P -H n H IE '1 74LVC109 Dual JK flip-flop with set and reset; positive-edge trigger Product specification Supersedes data of 1997 Mar 18 IC24 Data Handbook Philips Semiconductors 1998 Apr 28 PHILIPS Philips Semiconductors Product specification Dual JR flip-flop with set and reset; positive-edge trigger


    OCR Scan     		PDF 74LVC109 74LVC109 74HC/HCT109. 74LVC109t