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    JEDEC CP 20 Search Results

    JEDEC CP 20 Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    TMP139AIYAHR Texas Instruments JEDEC DDR5 temperature sensor with 0.5 °C accuracy 6-DSBGA -40 to 125 Visit Texas Instruments Buy
    SN74SSQEA32882ZALR Texas Instruments JEDEC SSTE32882 Compliant 28-Bit to 56-Bit Registered Buffer with Address-Parity Test 176-NFBGA 0 to 85 Visit Texas Instruments Buy
    SN74SSQE32882ZALR Texas Instruments JEDEC SSTE32882 Compliant 28-Bit to 56-Bit Registered Buffer with Address-Parity Test 176-NFBGA 0 to 85 Visit Texas Instruments
    SN74SSQEB32882ZALR Texas Instruments JEDEC SSTE32882 Compliant 28-Bit to 56-Bit Registered Buffer with Address-Parity Test 176-NFBGA 0 to 85 Visit Texas Instruments Buy
    SN74SSQEC32882ZALR Texas Instruments JEDEC SSTE32882 Compliant Low Power 28-Bit to 56-Bit Registered Buffer with Address-Parity Test 176-NFBGA 0 to 85 Visit Texas Instruments Buy

    JEDEC CP 20 Datasheets Context Search

    Catalog Datasheet MFG & Type Document Tags PDF

    4000B

    Abstract: 74HC4024 74HC4024D 74HC4024DB 74HC4024N 74HC4024PW
    Text: 74HC4024 7-stage binary ripple counter Product data sheet 1. General description The 74HC4024 is a high-speed Si-gate CMOS device and is pin compatible with the 4024 of the 4000B series. The 74HC4024 is specified in compliance with JEDEC standard no. 7A. The 74HC4024 is a 7-stage binary ripple counter with a clock input CP , an overriding


    Original     		74HC4024 74HC4024 4000B OT108-1 076E06 MS-012 74HC4024D 74HC4024DB 74HC4024N 74HC4024PW PDF

    74AC299

    Abstract: 74AC299MTC 74AC299PC 74AC299SC 74AC299SCX 74AC299SJ 74ACT299 74ACT299SC
    Text: Revised March 2005 74AC299 • 74ACT299 8-Input Universal Shift/Storage Register with Common Parallel I/O Pins General Description Features The AC/ACT299 is an 8-bit universal shift/storage register with 3-STATE outputs. Four modes of operation are possible: hold store , shift left, shift right and load data. The parallel load inputs and flip-flop outputs are multiplexed to


    Original     		74AC299 74ACT299 AC/ACT299 74AC299 74AC299MTC 74AC299PC 74AC299SC 74AC299SCX 74AC299SJ 74ACT299 74ACT299SC PDF

    74AC377

    Abstract: 74AC377MTC 74AC377MTCX 74AC377PC 74AC377SC 74AC377SJ 74ACT377 74ACT377SC 74ACT377 FAIRCHILD
    Text: Revised March 2005 74AC377 • 74ACT377 Octal D-Type Flip-Flop with Clock Enable General Description Features The AC/ACT377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock CP input loads all flip-flops simultaneously,


    Original     		74AC377 74ACT377 AC/ACT377 74AC377 74AC377MTC 74AC377MTCX 74AC377PC 74AC377SC 74AC377SJ 74ACT377 74ACT377SC 74ACT377 FAIRCHILD PDF

    74AC374

    Abstract: 74AC374MTC 74AC374PC 74AC374SC 74AC374SCX 74AC374SJ 74ACT374 74ACT374SC ACT374
    Text: Revised March 2005 74AC374 • 74ACT374 Octal D-Type Flip-Flop with 3-STATE Outputs General Description Features The AC/ACT374 is a high-speed, low-power octal D-type flip-flop featuring separate D-type inputs for each flip-flop and 3-STATE outputs for bus-oriented applications. A buffered Clock CP and Output Enable (OE) are common to


    Original     		74AC374 74ACT374 AC/ACT374 ACT374 74AC374 74AC374MTC 74AC374PC 74AC374SC 74AC374SCX 74AC374SJ 74ACT374 74ACT374SC PDF

    74AC163

    Abstract: 74AC163MTC 74AC163PC 74AC163SC 74AC163SJ 74ACT163 74ACT163SC 74ACT163SJ ACT163
    Text: Revised February 2000 74AC163 • 74ACT163 Synchronous Presettable Binary Counter General Description Features The AC/ACT163 are high-speed synchronous modulo-16 binary counters. They are synchronously presettable for application in programmable dividers and have two types


    Original     		74AC163 74ACT163 AC/ACT163 modulo-16 ACT163 74AC163 74AC163MTC 74AC163PC 74AC163SC 74AC163SJ 74ACT163 74ACT163SC 74ACT163SJ PDF

    74ACT377SJ

    Abstract: 74AC377 74AC377MTC 74AC377PC 74AC377SC 74AC377SJ 74ACT377 74ACT377SC
    Text: Revised June 2001 74AC377 • 74ACT377 Octal D-Type Flip-Flop with Clock Enable General Description Features The AC/ACT377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock CP input loads all flip-flops simultaneously,


    Original     		74AC377 74ACT377 AC/ACT377 74ACT377SJ 74AC377 74AC377MTC 74AC377PC 74AC377SC 74AC377SJ 74ACT377 74ACT377SC PDF

    Untitled

    Abstract: No abstract text available
    Text: Revised September 2003 74AC161 • 74ACT161 Synchronous Presettable Binary Counter General Description Features The AC/ACT161 are high-speed synchronous modulo-16 binary counters. They are synchronously presettable for application in programmable dividers and have two types


    Original     		74AC161 74ACT161 AC/ACT161 modulo-16 ACT161 74AC16THOUT PDF

    Binary counter simple 74ac161

    Abstract: 74AC161 74AC161MTC 74AC161PC 74AC161SC 74AC161SJ 74ACT161 74ACT161SC 74ACT161SJ ACT161
    Text: Revised September 2003 74AC161 • 74ACT161 Synchronous Presettable Binary Counter General Description Features The AC/ACT161 are high-speed synchronous modulo-16 binary counters. They are synchronously presettable for application in programmable dividers and have two types


    Original     		74AC161 74ACT161 AC/ACT161 modulo-16 ACT161 74AC161SHOUT Binary counter simple 74ac161 74AC161 74AC161MTC 74AC161PC 74AC161SC 74AC161SJ 74ACT161 74ACT161SC 74ACT161SJ PDF

    74F676

    Abstract: 74F676PC 74F676SC 74F676SPC M24B MS-001 MS-011 MS-013 N24A N24C
    Text: Revised January 2002 74F676 16-Bit Serial/Parallel-In, Serial-Out Shift Register General Description Features The 74F676 contains 16 flip-flops with provision for synchronous parallel or serial entry and serial output. When the Mode M input is HIGH, information present on the


    Original     		74F676 16-Bit 74F676 74F676PC 74F676SC 74F676SPC M24B MS-001 MS-011 MS-013 N24A N24C PDF

    74F676

    Abstract: 74F676PC 74F676SC 74F676SPC M24B MS-001 MS-011 MS-013 N24A N24C
    Text: Revised October 2000 74F676 16-Bit Serial/Parallel-In, Serial-Out Shift Register General Description Features The 74F676 contains 16 flip-flops with provision for synchronous parallel or serial entry and serial output. When the Mode M input is HIGH, information present on the


    Original     		74F676 16-Bit 74F676 74F676PC 74F676SC 74F676SPC M24B MS-001 MS-011 MS-013 N24A N24C PDF

    74AC399

    Abstract: 74AC399PC 74AC399SC 74ACT399 74ACT399MTC 74ACT399PC 74ACT399SC 74ACT399SJ M16A
    Text: Revised October 2000 74AC399 • 74ACT399 Quad 2-Port Register General Description Features The AC/ACT399 is the logical equivalent of a quad 2-input multiplexer feeding into four edge-triggered flip-flops. A common Select input determines which of the two 4-bit


    Original     		74AC399 74ACT399 AC/ACT399 74AC399SC 16-Lead MS-012, 74AC399PC 74AC399 74AC399PC 74AC399SC 74ACT399 74ACT399MTC 74ACT399PC 74ACT399SC 74ACT399SJ M16A PDF

    Untitled

    Abstract: No abstract text available
    Text: Revised October 2000 74AC399 • 74ACT399 Quad 2-Port Register General Description Features The AC/ACT399 is the logical equivalent of a quad 2-input multiplexer feeding into four edge-triggered flip-flops. A common Select input determines which of the two 4-bit


    Original     		74AC399 74ACT399 AC/ACT399 74AC399SC 16-Lead MS-012, 74AC399PC PDF

    74AC174PC

    Abstract: 74ACT174 74AC174 74AC174MTC 74AC174SC 74AC174SJ 74ACT174SC 74ACT174SJ
    Text: Revised October 2000 74AC174 • 74ACT174 Hex D-Type Flip-Flop with Master Reset General Description Features The AC/ACT174 is a high-speed hex D-type flip-flop. The device is used primarily as a 6-bit edge-triggered storage register. The information on the D inputs is transferred to


    Original     		74AC174 74ACT174 AC/ACT174 ACT174 74AC174SC 16-Lead MS-012, 74AC174SJ 74AC174MTHOUT 74AC174PC 74ACT174 74AC174 74AC174MTC 74AC174SC 74AC174SJ 74ACT174SC 74ACT174SJ PDF

    Untitled

    Abstract: No abstract text available
    Text: Revised October 2000 74AC174 • 74ACT174 Hex D-Type Flip-Flop with Master Reset General Description Features The AC/ACT174 is a high-speed hex D-type flip-flop. The device is used primarily as a 6-bit edge-triggered storage register. The information on the D inputs is transferred to


    Original     		74AC174 74ACT174 AC/ACT174 ACT174 74AC174SC 16-Lead MS-012, 74AC174SJ 74AC17ITHOUT PDF

    JEDEC Code

    Abstract: JEDEC max1918 package outline weight EIAJ 133-AA JEDEC CP 28 MO133A
    Text: Package Outline Dimensions 24 16.90 17.27 Max 19 18 î n r - in 13 n n n r - ii- in 6 7 0.74 12 Hitachi code JEDEC code EIAJ code Weight g CP-24DB MO-077AA SC-632-A 0.80 9.40 ± 0.25 Hitachi code JEDEC code EIAJ code Weight (g) CP-28DA MO-061 AA SC-637-B


    OCR Scan     		CP-24DB MO-077AA SC-632-A CP-28DA MO-061 SC-637-B CP-42D TTP-28DA MO-133AA TTP-44DE JEDEC Code JEDEC max1918 package outline weight EIAJ 133-AA JEDEC CP 28 MO133A PDF

    Am29C82

    Abstract: No abstract text available
    Text: Am29C821 / Am29C823 Am29C921 /Am29C923 High-Performance CMOS Bus Interface Registers High-speed parallel positive edge-triggered registers with D-type flip-flops - CP-Y propagation delay = 8 ns typical • Low standby power • JEDEC FCT-compatible specs •


    OCR Scan     		Am29C821 Am29C823 Am29C921 /Am29C923 /Am29C823 Am29C921/Am29C923 10-bit) Am29C900 Am29C82 PDF

    Am29CB21

    Abstract: am29c800 cis 11-pin Am29C821
    Text: Am29C821 / Am29C823 Am29C921 / Am29C923 High-Performance CMOS Bus Interface Registers • • • High-speed parallel positive edge-triggered registers with D-type flip-flops - CP-Y propagation delay - 8 ns typical Low standby power JEDEC FCT-compatible specs


    OCR Scan     		Am29C821 Am29C823 Am29C921 Am29C923 Am29C821/ Am29C921/ 10-bit) Am29C900 Am29CB21 am29c800 cis 11-pin PDF

    amd am2 pinout

    Abstract: AM29C821/B3A pinout AM2 AMD CD3024 PD3024 AM29C823 AM29C821PC
    Text: Am29C821 / Am29C823 Am29C921 /Am29C923 High-Performance CMOS Bus Interface Registers High-speed parallel positive edge-triggered registers with D-type flip-flops - CP-Y propagation delay = 8 ns typical • Low standby power • JEDEC FCT-compatible specs •


    OCR Scan     		Am29C821 Am29C823 Am29C921 Am29C923 10-bit) Am29C900 AIS-WCP-20M-01/88-0 amd am2 pinout AM29C821/B3A pinout AM2 AMD CD3024 PD3024 AM29C821PC PDF

    CD3024

    Abstract: PD3024 AM29C821PC
    Text: Am29C821 / Am29C823 Am29C921 /Am29C923 High-Performance C M O S Bus Interface Registers High-speed parallel positive edge-triggered registers with D-type flip-flops - CP-Y propagation delay = 8 ns typical • Low standby power • JEDEC FCT-compatible specs


    OCR Scan     		Am29C821/Am29C823 Am29C921 Am29C923 10-bit) Am29C900 Am29C821 Am29C823 Am29C800 CS-11 AIS-WCP-20M-01/88-0 CD3024 PD3024 AM29C821PC PDF

    SN54AHCT128

    Abstract: No abstract text available
    Text: SN54AHCT126, SN74AHCT126 QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS SCLS265B - DECEMBER 1995 - REVISED JULY 1996 Inputs Are TTL-Voitage Compatible CP/C Enhanced-Performance Implanted CMOS Process High Latch-Up Immunity Exceeds 250 mA Per JEDEC Standard JESD-17


    OCR Scan     		SN54AHCT126, SN74AHCT126 SCLS265B JESD-17 300-mil AHCT126 SN54AHCT128 PDF

    Untitled

    Abstract: No abstract text available
    Text: SN54AHC04, SN74AHC04 HEX INVERTERS SCLS231C - OCTOBER 1995 - REVISED MARCH 1996 • • • • Operating Range 2-V to 5.5-V V jC CP/C (Enhanced-Performance Implanted CMOS Process High Latch-Up Immunity Exceeds 250 mA Per JEDEC Standard JESD-17 ESD Protection Exceeds 2000 V Per


    OCR Scan     		SN54AHC04, SN74AHC04 SCLS231C JESD-17 MIL-STD-883C, 300-mll SN54AHC04 SN74AHC04 PDF

    Untitled

    Abstract: No abstract text available
    Text: Definition of Specifications 1. Power Dissipation - Test Philosophy In an erfort to reduce confusion about measuring Cp d , a JEDEC standard test procedure 7A Appendix E has been adopted, which specifies the test setup for each type o f device. This allows a


    OCR Scan     		PDF

    Untitled

    Abstract: No abstract text available
    Text: SN54AHC00, SN74AHC00 QUADRUPLE 2-INPUT POSITIVE-NAND GATES S C LS 227A -OCTOBER 1995 - REVISED MARCH 1996 Operating Range 2-V to 5.5-V Vcc CP/C Enhanced-Performance Implanted CMOS Proceas High Latch-Up Immunity Exceeds 250 mA Per JEDEC Standard JESD-17


    OCR Scan     		SN54AHC00, SN74AHC00 JESD-17 MIL-STD-883C, 300-mil AHC00 SN54AHC00 PDF

    Untitled

    Abstract: No abstract text available
    Text: cP ÏITSU May 1997 Revision 1.0 SDC4UV7282C- 67/84/100/125 T-S 32MByte (4M x 72) CMOS Synchronous DRAM Module - ECC General Description The SDC4UV7282C-(67/84/100/125)T-S is a high performance, 32-megabtye synchronous, dynamic RAM module organized as 4M words by 72 bits, in a 168-pin, JEDEC ECC configuration, dual-in-line memory module (DIMM) package.


    OCR Scan     		SDC4UV7282C- 32MByte 32-megabtye 168-pin, MB81117822A- 374175b PDF