Untitled
Abstract: No abstract text available
Text: December 1999 GENERAL DESCRIPTION The HI-8482 bus interface unit is a silicon gate CMOS device designed as a dual line receiver in accordance with the requirements of the ARINC 429 bus specification. It contains two independent ARINC receiver channels which accept differential input signals and converts them
|
Original
|
PDF
|
HI-8482
RM3183.
20-PIN
|
DS8482
Abstract: HI-8482 raytheon analog 8 pin dip
Text: June 2000 GENERAL DESCRIPTION The HI-8482 bus interface unit is a silicon gate CMOS device designed as a dual differential line receiver in accordance with the requirements of the ARINC 429 bus specification. The device translates incoming ARINC 429 signals to normal CMOS/TTL levels on each of its two independent receive channels. The HI-8482 is also functionally equivalent to the Fairchild/Raytheon RM3183.
|
Original
|
PDF
|
HI-8482
RM3183.
20-PIN
DS8482
raytheon analog 8 pin dip
|
CERAMIC LEADLESS CHIP CARRIER package
Abstract: HI-8482 HI-8482CM DS8482
Text: January 2001 GENERAL DESCRIPTION The HI-8482 bus interface unit is a silicon gate CMOS device designed as a dual differential line receiver in accordance with the requirements of the ARINC 429 bus specification. The device translates incoming ARINC 429 signals to normal CMOS/TTL levels on each of its two independent receive channels. The HI-8482 is also functionally equivalent to the Fairchild/Raytheon RM3183.
|
Original
|
PDF
|
HI-8482
RM3183.
20-PIN
CERAMIC LEADLESS CHIP CARRIER package
HI-8482CM
DS8482
|
HI-8482PSI
Abstract: HI-8482 HI-8482PST HI-8482CM-01 CERAMIC LEADLESS CHIP CARRIER package DPLC HI-6010 HI-8482J HI-8482JT HI-8683
Text: February 2001 GENERAL DESCRIPTION The HI-8482 bus interface unit is a silicon gate CMOS device designed as a dual differential line receiver in accordance with the requirements of the ARINC 429 bus specification. The device translates incoming ARINC 429 signals to normal CMOS/TTL levels on each of its two independent receive channels. The HI-8482 is also functionally equivalent to the Fairchild/Raytheon RM3183.
|
Original
|
PDF
|
HI-8482
RM3183.
HI-8482J
HI-8482JT
20-PIN
HI-8482PSI
HI-8482PST
HI-8482CM-01
CERAMIC LEADLESS CHIP CARRIER package
DPLC
HI-6010
HI-8482J
HI-8482JT
HI-8683
|
HI-8482
Abstract: No abstract text available
Text: HI-8482 ARINC 429 DUAL LINE RECEIVER The self-test inputs force the outputs to either a ZERO, ONE, or NULL state for system tests. While in self-test mode, the ARINC inputs are ignored. IN2B - 4 OUT2B - 5 IN2A - 6 CAP2A - 7 OUT2A - 8 All the ARINC inputs have built-in hysteresis to reject
|
Original
|
PDF
|
HI-8482
HI-8482
RM3183.
20-PIN
|
HI-8482
Abstract: 8482
Text: HI-8482 ARINC 429 DUAL LINE RECEIVER OUT2A - 8 The HI-8482 line receiver is one of several options offered by Holt Integrated Circuits to interface to the ARINC bus. The digital data processing for serial-to-parallel conversion and clock recovery can be accomplished with the
|
Original
|
PDF
|
HI-8482
HI-8482
RM3183.
20-PIN
8482
|
Fusion29K
Abstract: Am29040 Am29030 AM29035 EZ-030 ID10 ID12 ID16 Am29030-25GC AM29035-16FC
Text: PRELIMINARY Am29030 and Am29035 RISC Microprocessors with 8-Kbyte/4-Kbyte Instruction Cache Advanced Micro Devices Am29030 MICROPROCESSOR DISTINCTIVE CHARACTERISTICS Full 32-bit architecture 8-, 16-, or 32-bit ROM interface 26 million instructions per second MIPS
|
Original
|
PDF
|
Am29030TM
Am29035TM
Am29030
32-bit
64-entry
25-MHz
Am29005Tontains
Am29000
Fusion29K
Am29040
AM29035
EZ-030
ID10
ID12
ID16
Am29030-25GC
AM29035-16FC
|
HI-8482
Abstract: No abstract text available
Text: HI-8482 ARINC 429 DUAL LINE RECEIVER OUT2A - 8 The HI-8482 line receiver is one of several options offered by Holt Integrated Circuits to interface to the ARINC bus. The digital data processing for serial-to-parallel conversion and clock recovery can be accomplished with the
|
Original
|
PDF
|
HI-8482
HI-8482
RM3183.
20-PIN
|
ic 7493 truth table
Abstract: HI-8482 HI-6010 HI-8482J HI-8482JT HI-8482PSI HI-8482PST HI-8683 RM3183 DS8482
Text: HI-8482 ARINC 429 Dual Line Receiver March 2007 OUT2A - 8 The HI-8482 line receiver is one of several options offered by Holt Integrated Circuits to interface to the ARINC bus. The digital data processing for serial-to-parallel conversion and clock recovery can be accomplished with the
|
Original
|
PDF
|
HI-8482
HI-8482
HI-6010,
HI-8683
ARIN80
20-PIN
ic 7493 truth table
HI-6010
HI-8482J
HI-8482JT
HI-8482PSI
HI-8482PST
RM3183
DS8482
|
HI-8482CM-01
Abstract: HI-8482 HI-8482PSI HI-6010 HI-8482J HI-8482JT HI-8482PST HI-8683 RM3183 DS8482
Text: HI-8482 ARINC 429 DUAL LINE RECEIVER OUT2A - 8 The HI-8482 line receiver is one of several options offered by Holt Integrated Circuits to interface to the ARINC bus. The digital data processing for serial-to-parallel conversion and clock recovery can be accomplished with the
|
Original
|
PDF
|
HI-8482
HI-8482
HI-6010,
HI-8683
20-PIN
HI-8482CM-01
HI-8482PSI
HI-6010
HI-8482J
HI-8482JT
HI-8482PST
RM3183
DS8482
|
QC-080324-WZ
Abstract: QC-304333-WZ QC-080333-WZ QC-160345-WZ QC-100364-WZ QC-240326-WZ QC-304304-WZ KKC-10497 QC-064347-WZ 256319
Text: KYOCERA CERQUAD PACKAGES Notes 1 Die Attach Cavity Option: Bare Ceramic Surface or Gold Paste (2) Leadframe Surface Finish Option: Aluminum Thin Film Deposition on Wire Bond Area or Electrolytic Gold Plating on All the Surface of Leadframes (3) CERQUAD is a registered trademark of KYOCERA Corporation.
|
Original
|
PDF
|
R0165B
QC-080324-WZ
QC-304333-WZ
QC-080333-WZ
QC-160345-WZ
QC-100364-WZ
QC-240326-WZ
QC-304304-WZ
KKC-10497
QC-064347-WZ
256319
|
PLL VCO MIL-PRF-38535
Abstract: TSPC603R D-H19 msr 206 pinout
Text: Features • • • • • • • • 5.6 SPECint95, 4 SPECfp95 and 200 MHz Estimated Superscalar (3 Instructions per Clock Peak) Dual 16 KB Caches Selectable Bus Clock 32-bit Compatibility PowerPC Implementation On-Chip Debug Support PD Typically = 2.5W (200 MHz), Full Operating Conditions
|
Original
|
PDF
|
SPECint95,
SPECfp95
32-bit
PID7t-603e
PLL VCO MIL-PRF-38535
TSPC603R
D-H19
msr 206 pinout
|
MQUAD
Abstract: PowerPC-603e 603E
Text: Features H H H H H H H H 5.6 SPECint95, 4.0 SPECfp95 @ 200 MHz estimated Superscalar (3 instructions per clock peak). Dual 16KB caches. Selectable bus clock. 32-bit compatibility PowerPC implementation. On chip debug support. PD typical = 2.5 Watts (200 MHz), full operating conditions.
|
Original
|
PDF
|
SPECint95,
SPECfp95
32-bit
PID7t-603e
PowerPC603e
TSPC603r
MQUAD
PowerPC-603e
603E
|
TEA 2025 equivalent
Abstract: atmel 528 24 c01 abb main switch ABB 14 11 09 Tag 225 600 replacement TMS 320 C 6X processor datasheet JESD51-2 TSPC603R atmel part marking c08
Text: Features • • • • • • • Superscalar 3 Instructions per Clock Peak Dual 16 KB Caches Selectable Bus Clock 32-bit Compatibility PowerPC Implementation On-chip Debug Support Nap, Doze and Sleep Power Saving Modes Device Offered in Cerquad, CBGA 255, HiTCE CBGA 255 and CI-CGA 255
|
Original
|
PDF
|
32-bit
SPECint95,
SPECfp95
64-bit
5410B
TSPC603R
TEA 2025 equivalent
atmel 528 24 c01
abb main switch
ABB 14 11 09
Tag 225 600 replacement
TMS 320 C 6X processor datasheet
JESD51-2
TSPC603R
atmel part marking c08
|
|
PC603R
Abstract: atmel 528 24 c01 TSPC603R 255l K12K14 NS615
Text: Features • • • • • • • Superscalar 3 Instructions per Clock Peak Dual 16 KB Caches Selectable Bus Clock 32-bit Compatibility PowerPC Implementation On-chip Debug Support Nap, Doze and Sleep Power Saving Modes Device Offered in Cerquad, CBGA 255 and CI-CGA 255
|
Original
|
PDF
|
32-bit
SPECint95,
SPECfp95
64-bit
PC603R
atmel 528 24 c01
TSPC603R
255l
K12K14
NS615
|
emcp
Abstract: JEDEC JESD51-8 BGA CI-CGA-255
Text: TSPC603R PowerPC 603e RISC Microprocessor Family PID7t-603e Datasheet Features • • • • • • • Superscalar 3 Instructions per Clock Peak Dual 16 KB Caches Selectable Bus Clock 32-bit Compatibility PowerPC Implementation On-chip Debug Support
|
Original
|
PDF
|
TSPC603R
PID7t-603e
32-bit
SPECint95,
SPECfp95
64-bit
0841D
emcp
JEDEC JESD51-8 BGA
CI-CGA-255
|
HI-8482
Abstract: No abstract text available
Text: HI-8482 HOLE INTEGRATED CIRCUITS ARINC 429 DUAL LINE RECEIVER PIN CONFIGURATIONS GENERAL DESCRIPTION The HI-8482 bus interface unit is a silicon gate CMOS de vice designed as a dual line receiver in accordance with the requirements of the ARINC 429 bus specification. It
|
OCR Scan
|
PDF
|
HI-8482
HI-8482
RM3183.
|
H1848
Abstract: No abstract text available
Text: HOLT, HI-8482 INTEGRATED CIRCUITS ARINC 429 DUAL LINE RECEIVER PIN CONFIGURATIONS GENERAL DESCRIPTION The HI-8482 bus interface unit is a silicon gate CMOS de vice designed as a dual line receiver in accordance with the requirements of the ARINC 429 bus specification. It
|
OCR Scan
|
PDF
|
HI-8482
HI-8482
theRM3183.
20-PIN
H1848
|
ID31
Abstract: Am29030 EZ-030 AMD 29040
Text: a PRELIMINARY •TM Am29030 and Am29035 RISC Microprocessors with 8-Kbyte/4-Kbyte Instruction Cache Advanced Micro Devices Am29030 MICROPROCESSOR DISTINCTIVE CHARACTERISTICS ■ Full 32-bit architecture ■ 8-, 16-, or 32-bit ROM interface ■ 26 million instructions per second MIPS
|
OCR Scan
|
PDF
|
Am29030TM
Am29035
Am29030
32-bit
25-MHz
64-entry
Fusion29K
Am29005
ID31
EZ-030
AMD 29040
|
ID19
Abstract: No abstract text available
Text: PRELIMINARY Am29030 and Am29035™ Advanced Micro Devices RISC Microprocessors with 8-Kbyte/4-Kbyte Instruction Cache Am29030 MICROPROCESSOR DISTINCTIVE CHARACTERISTICS • Full 32-bit architecture ■ 8-, 16-, or 32-bit ROM interface ■ 26 million instructions per second MIPS
|
OCR Scan
|
PDF
|
Am29030TM
Am29035TM
Am29030
32-bit
25-MHz
64-entry
7447A
Fusion29K
ID19
|
14C14
Abstract: EZ-030 Ez03 AM29035 H-14 2903-03 A20122 A 3140 opto AM29005 ID23
Text: PRELIMINARY Am29030 and Am29035™ RISC Microprocessors with 8-Kbyte/4-Kbyte Instruction Cache Advanced Micro Devices Am29030 MICROPROCESSOR DISTINCTIVE CHARACTERISTICS • ■ ■ ■ ■ ■ Full 32-bit architecture 26 million instructions per second MIPS
|
OCR Scan
|
PDF
|
Am29030
Am29035
32-bit
25-MHz
64-entry
Fusion29K
Am29000
14C14
EZ-030
Ez03
H-14
2903-03
A20122
A 3140 opto
AM29005
ID23
|
Untitled
Abstract: No abstract text available
Text: Tem ic DG535/536 Semiconductors 16-Channel Wideband Video Multiplexers Features • • • • • • • Crosstalk: -100 dB @ 5 MHz 300 MHz Bandwidth Low Input and Output Capacitance Low Power: 75 fiW Low r DS on : 50 Q On-Board Address Latches Disable Output
|
OCR Scan
|
PDF
|
DG535/536
16-Channel
DG535/536
DG536
aMC14504B.
DG536.
P-32167--Rev.
15-Nov-93
|
Untitled
Abstract: No abstract text available
Text: SPT SIGNAL PROCESSING TECHNOLOGIES SPT7870 10-BIT, 100 MSPS ECL A/D CONVERTER PRELIMINARY INFORMATION FEATURES APPLICATIONS 10-Bit, 100 MSPS Analog-to-Digital Converter Monolithic Bipolar Single-Ended Bipolar Analog Input -1.0 V to +1.0 V Analog Input Range
|
OCR Scan
|
PDF
|
SPT7870
10-BIT,
SPT7871
SPT7870
|
Untitled
Abstract: No abstract text available
Text: & SPT SPT7B70 10-BIT, 100 MSPS ECL A/D CONVERTER SIGNAL PROCESSING TECHNOLOGIES PRELIMINARY INFORMATION FEATURES APPLICATIONS • • • • • • • • • • • • • • 10-Bit, 100 MSPS Ana!og-to-Digital Converter Monolithic Bipolar Single-Ended Bipolar Analog Input
|
OCR Scan
|
PDF
|
SPT7B70
10-BIT,
SPT7871
SPT7870
SPT7870SIJ
SPT7870SIQ
SPT7870SCU
|