IRO118LC1B

Contextual Info: 1 TO 18 GHz IMAGE REJECTION OR I/Q MIXERS MODELS: IR0118LC1A, IRO118LC1B, IRO118LC1C AND IRO118LC1Q FEATURES • RF/LO Coverage . 1 to 18 GHz • IF Operation . DC to 0.5 GHz • LO Power Range . +10 to +13 dBm • Conversion Loss . 10 dB Typical

IR014

Abstract: WD37C65 WD76C10 WD76C30 intel 80287 ir037 84-PIN WD16C450 WD16C452 WD16C552
Contextual Info: I. . WD76C30lLV TABLE OF CONTENTS Section Title 1.0 DESCRIPTION 1.1 Features 1.2 General 1.3 WD76C30/LV Differences 1.4 Peripheral Controller 6-1 6-1 6-1 6-1 6-2 2.0 PIN DESCRIPTION 6-3 3.0 SERIAL PORT REGISTERS 3.1 Serial Port Register Addressing 3.1.1

d472 TRANSISTOR

Abstract: transistor d472 IT191 WD76C10A t2146 wd90c90 floppy disk chip d472 TRANSISTOR equivalent WD76C10ALP i8042
Contextual Info: WD76C1 OAILPIL V TABLE OF CONTENTS Section Title 1.0 INTRODUCTION 1.1 Document Scope 1.2 Features 1.3 General Description 1.3.1 WD76C10A 1.3.2 WD76C10ALP 1.3.3 WD76C10ALV 4-1 4-1 4-1 4-1 4-1 4-2 4-2 2.0 ARCHITECTURE 2.1 Initialization And Clocking 2.2 AT Bus . . . . . . .

SE82365SL

Abstract: SFH 6711 Lm 7011 Z365
Contextual Info: O K I Semiconductor Z36S PCM CIA 0.8|im T ech n olo gy M ega M acrocell DESCRIPTION The 2365 PCMCIA Mega Macrocell is a featured library element in OKI's 0.8|im Sea of Cates and 0.8|im Customer Structured Array families. The OKI implementation of the Mega Macrocell is fully compatible

Contextual Info: • DESCRIPTION The MB86$30 is a 16-bit fixed-point DSP Digital Signal Processor that is based on Fujitsu-specific Dual-MAC architecture, and can implement product addition operations and double transfer at a high rate and under low power consumption. The DSP supports a set of instructions optimum for digital signal processing in communications applications such

IR0208

Abstract: IR0218LC1 ir020 IR0204LC2 IR0812LC2
Contextual Info: IMAGE REJECTION MIXERS AND I/Q DEMODULATORS IR IF HYBRID VCC IR IR Image Rejection MODEL NUMBER IRF MESFET Image Rejection FREQUENCY RANGE IF RF AND LO GHz (GHz) (Note 1) NOMINAL LO POWER (dBm) (Note 2) IRB Biasable Image Rejection CONVERSION LOSS (dB) (Max.)

IR0218LC1

Abstract: IR0502LC1 IR0204LC2 IR0618LC2 IR0812LC2
Contextual Info: IMAGE REJECTION MIXERS AND I/Q DEMODULATORS IR IF HYBRID VCC IR IR Image Rejection MODEL NUMBER IRF MESFET Image Rejection FREQUENCY RANGE IF RF AND LO GHz (GHz) (Note 1) NOMINAL LO POWER (dBm) (Note 2) IRB Biasable Image Rejection CONVERSION LOSS (dB) (Max.)

a872 TRANSISTOR equivalent

Abstract: d472 TRANSISTOR d472 TRANSISTOR equivalent transistor d472 IT191 power generation POWER COMMAND HM 1211 WD90C90 LT242 POWER COMMAND HM 1211 floppy disk chip
Contextual Info: WD771 OIWD771 OLP TABLE OF CONTENTS Section Title 1.0 INTRODUCTION 1.1 Document Scope 1.2 Features 1.3 General Description 1.3.1 WD7710 1.3.2 WD7710lP 7-1 7-1 7-1 7-2 7-2 7-2 2.0 ARCHITECTURE 2.1 Initialization And Clocking AT Bus . . . . . . . 2.2 Main Processor Control

Contextual Info: ß fö H O M O K lM lf intei M82380 HIGH PERFORMANCE 32-BIT DMA CONTROLLER WITH INTEGRATED SYSTEM SUPPORT PERIPHERALS High Performance 32-Bit DMA Controller — 40 MBytes/sec Maximum Data Transfer Rate at 20 MHz — 8 Independently Programmable Channels DRAM Refresh Controller

386DX bios

Abstract: JCA Technology 486SX 486DX 386DX 486 SA SX 486 system bus notebook 486 MS400 486DX BIOS
Contextual Info: MOSEL MS400 486SX / 486DX Single Chip AT PRELIMINARY FEATURES DESCRIPTION • Direct Interface to 486SX/487SX or 486DX at speeds from 20-33MHZ The MS400 is a highly integrated single chip AT opti­ mized specifically for 486 CPUs. Emphasis has been placed on the cost reduction requirements of 486SX

P82C206

Abstract: f82c206 82C206 KZh Series CS8220 244jjs 8254 cascading 74LS612 MC146818 82C206-INTEGRATED
Contextual Info: PRELIMINARY 82C 206 IN T E G R A T E D P E R IP H E R A L S C O N TR O LLER • 100% Compatible to IBM'" PC AT 114 bytes of CM O S RAM memory ■ Fully com patible to Intel'“’s 8237 DMA controller, 8259 Interrupt controller, 8254 Tim er/Counter, and Motorola""« 146818

ORCAT

Abstract: SE82365SL IR014 OKI D51 rtl 8112 MSM98S000 Z365 00WS 5CTI 51ti
Contextual Info: O K I Semiœnductor Z365 PCMCIA 0.8|jm T e c h n o lo g y Mega M acrocell DESCRIPTION The 2365 PCMCIA Mega Macrocell is a featured library element in OKI's 0.8p,m Sea of Gates and 0.8|im Customer Structured Array families. The OKI implementation of the Mega Macrocell is fully compatible

smdt 002

Abstract: IR029 IR024 ir020 ir022 IR026 IR028 IR027 IR016 ir030
Contextual Info: Processor Digital Signal Processor 16-bit Fixed-point DSP MB86330 DESCRIPTION The MB86330 is a 16-bit fixed-point DSP Digital Signal Processor that is based on Fujitsu-specific Dual-MAC architecture, and can implement product addition operations and double transfer at a high rate and under low

VIA VT82C686A GPIO

Contextual Info: WMmkTOefiAmea MWW&Teclinologies. VT82C686A VT82C686A PSIPC P C I S u p e r -I/O I n t e g r a t e d P e r ip h e r a l C o n t r o l l e r P C 9 8 C o m p l ia n t P C I- t o -IS A B r id g e w it h I n t e g r a t e d S u p e r -I/O F D C , L P T , C o m 1 /2, a n d IR ,