Advanced Boot Block Flash
Abstract: AES-128 CS201 CS281 CS289 AGLP125
Text: v1.5 IGLOO PLUS Low-Power Flash FPGAs with Flash*Freeze Technology Features and Benefits Low Power • • • • • 1.2 V to 1.5 V Core Voltage Support for Low Power Supports Single-Voltage System Operation 5 µW Power Consumption in Flash*Freeze Mode
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130-nm,
Advanced Boot Block Flash
AES-128
CS201
CS281
CS289
AGLP125
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QN68
Abstract: VQ100 actel part markings
Text: Advance v0.4 ProASIC®3 nano Flash FPGAs Features and Benefits Advanced I/Os Wide Range of Features • 10 k to 250 k System Gates • Up to 36 kbits of True Dual-Port SRAM • Up to 71 User I/Os Reprogrammable Flash Technology • • • • 130-nm, 7-Layer Metal 6 Copper , Flash-Based CMOS Process
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PDF
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130-nm,
128-Bit
QN68
VQ100
actel part markings
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actel vqfp
Abstract: IO87RSB1
Text: ProASIC3 nano Packaging 3 – Package Pin Assignments 48-Pin QFN Pin 1 48 1 Notes: 1. This is the bottom view of the package. 2. The die attach paddle of the package is tied to ground GND . Note For Package Manufacturing and Environmental information, visit the Resource Center at
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PDF
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48-Pin
A3PN010
GEC0/IO37RSB1
IO06RSB0
IO36RSB1
GDA0/IO05RSB0
GEA0/IO34RSB1
actel vqfp
IO87RSB1
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IO91RSB2
Abstract: Datasheet AGLN060 81-Pin Datasheet AGLN020 AGLN020 IO10RSB0 AGLN010
Text: IGLOO nano Packaging 3 – Package Pin Assignments 36-Pin UC Pin 1 Pad Corner 6 5 4 3 2 1 A B C D E F Note: This is the bottom view of the package. Note For Package Manufacturing and Environmental information, visit the Resource Center at .
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36-Pin
AGLN010
IO21RSB1
IO18RSB1
IO13RSB1
GDC0/IO00RSB0
IO06RSB0
GDA0/IO04RSB0
GEC0/IO37RSB1
IO91RSB2
Datasheet AGLN060
81-Pin
Datasheet AGLN020
AGLN020
IO10RSB0
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QN68
Abstract: VQ100 PAC11 ProASIC3 handbook
Text: Advance v0.5 ProASIC®3 nano Flash FPGAs Features and Benefits Advanced I/Os Wide Range of Features • 10 k to 250 k System Gates • Up to 36 kbits of True Dual-Port SRAM • Up to 71 User I/Os Reprogrammable Flash Technology • • • • 130-nm, 7-Layer Metal 6 Copper , Flash-Based CMOS Process
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Original
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PDF
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130-nm,
128-Bit
QN68
VQ100
PAC11
ProASIC3 handbook
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CPLD
Abstract: CS-289
Text: Revision 14 IGLOO PLUS Low Power Flash FPGAs with Flash*Freeze Technology Features and Benefits Advanced I/O Low Power • • • • • 1.2 V to 1.5 V Core Voltage Support for Low Power Supports Single-Voltage System Operation 5 µW Power Consumption in Flash*Freeze Mode
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Untitled
Abstract: No abstract text available
Text: Product Brief 1 – IGLOO PLUS Low-Power Flash FPGAs with Flash*Freeze Technology Features and Benefits High-Performance Routing Hierarchy Low Power Advanced I/O • Segmented, Hierarchical Routing and Clock Structure • • • • • 1.2 V or 1.5 V Core Voltage for Low Power
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Untitled
Abstract: No abstract text available
Text: IGLOO nano Handbook IGLOO nano Handbook Table of Contents Low-Power Flash Device Handbooks Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i Section I – IGLOO nano Datasheet IGLOO nano Low-Power Flash FPGAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
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Actel igloo
Abstract: Datasheet AGLN020 CS81 VQ100 RAM51 AGLN010
Text: Advance v0.8 IGLOO nano Low-Power Flash FPGAs with Flash*Freeze Technology Features and Benefits High-Performance Routing Hierarchy Low Power Advanced I/Os • Segmented, Hierarchical Routing and Clock Structure • • • • • nanoPower Consumption—Industry’s Lowest Power
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71most
Actel igloo
Datasheet AGLN020
CS81
VQ100
RAM51
AGLN010
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Untitled
Abstract: No abstract text available
Text: Revision 9 ProASIC3 nano Flash FPGAs Features and Benefits Advanced I/Os • 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation • Bank-Selectable I/O Voltages—up to 4 Banks per Chip • Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V / 2.5 V / 1.8 V / 1.5 V
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Untitled
Abstract: No abstract text available
Text: Revision 13 IGLOO nano Low Power Flash FPGAs with Flash*Freeze Technology Features and Benefits High-Performance Routing Hierarchy Low Power Advanced I/Os • Segmented, Hierarchical Routing and Clock Structure • • • • • nanoPower Consumption—Industry’s Lowest Power
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Untitled
Abstract: No abstract text available
Text: Revision 10 ProASIC3 nano Flash FPGAs Features and Benefits Advanced I/Os • 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation • Bank-Selectable I/O Voltages—up to 4 Banks per Chip • Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V / 2.5 V / 1.8 V / 1.5 V
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PDF
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Untitled
Abstract: No abstract text available
Text: Revision 11 ProASIC3 nano Flash FPGAs Features and Benefits Advanced I/Os • 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation • Bank-Selectable I/O Voltages—up to 4 Banks per Chip • Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V / 2.5 V / 1.8 V / 1.5 V
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PDF
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Untitled
Abstract: No abstract text available
Text: Advance v0.3 ProASIC®3 nano Flash FPGAs Features and Benefits Advanced I/Os Wide Range of Features • 10 k to 250 k System Gates • Up to 36 kbits of True Dual-Port SRAM • Up to 71 User I/Os Reprogrammable Flash Technology • • • • 130-nm, 7-Layer Metal 6 Copper , Flash-Based CMOS Process
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origin SEMICONDUCTOR
Abstract: No abstract text available
Text: IGLOO nano Handbook IGLOO nano Handbook Table of Contents Low-Power Flash Device Handbooks Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i Section I – IGLOO nano Datasheet IGLOO nano Low-Power Flash FPGAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
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A3P010
Abstract: No abstract text available
Text: Advance v0.2 ProASIC®3 nano Flash FPGAs Features and Benefits Advanced I/Os Wide Range of Features • 10 k to 250 k System Gates • Up to 36 kbits of True Dual-Port SRAM • Up to 71 User I/Os Reprogrammable Flash Technology • • • • 130-nm, 7-Layer Metal 6 Copper , Flash-Based CMOS Process
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lookup table
Abstract: AES-128 CS201 CS281 CS289 Thin Quad flat package smartpower
Text: Revision 11 IGLOO PLUS Low Power Flash FPGAs with Flash*Freeze Technology Features and Benefits Advanced I/O Low Power • • • • • 1.2 V to 1.5 V Core Voltage Support for Low Power Supports Single-Voltage System Operation 5 µW Power Consumption in Flash*Freeze Mode
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Original
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PDF
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130-nm,
lookup table
AES-128
CS201
CS281
CS289
Thin Quad flat package
smartpower
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QN68
Abstract: VQ100 actel 0841 actel part markings
Text: Advance v0.6 ProASIC®3 nano Flash FPGAs Features and Benefits Advanced I/Os Wide Range of Features • 10 k to 250 k System Gates • Up to 36 kbits of True Dual-Port SRAM • Up to 71 User I/Os Reprogrammable Flash Technology • • • • 130-nm, 7-Layer Metal 6 Copper , Flash-Based CMOS Process
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Original
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PDF
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130-nm,
128-Bit
QN68
VQ100
actel 0841
actel part markings
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actel part markings
Abstract: qfn132 Datasheet AGLN020 Datasheet AGLN060 CS81 VQ100 AGLN010
Text: Advance v0.7 IGLOO nano Low-Power Flash FPGAs with Flash*Freeze Technology Features and Benefits Advanced I/Os • 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation • Bank-Selectable I/O Voltages—up to 4 Banks per Chip • Single-Ended I/O Standards: LVTTL, LVCMOS
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PDF
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JESD8-12,
actel part markings
qfn132
Datasheet AGLN020
Datasheet AGLN060
CS81
VQ100
AGLN010
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100 pin vqfp drawing
Abstract: actel package mechanical drawing 289-pin IO95RSB2 actel vqfp
Text: IGLOO PLUS Packaging 3 – Package Pin Assignments 128-Pin VQFP 128 1 128-Pin VQFP Note: This is the bottom view of the package. Note For Package Manufacturing and Environmental information, visit the Resource Center at .
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128-Pin
128-Pin
AGLP030
IO119RSB3
IO86RSB2
100 pin vqfp drawing
actel package mechanical drawing
289-pin
IO95RSB2
actel vqfp
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MARKING 9AB
Abstract: A3PN030Z A3PN250Z
Text: Revision 8 ProASIC3 nano Flash FPGAs Features and Benefits Advanced I/Os Wide Range of Features • 10 k to 250 k System Gates • Up to 36 kbits of True Dual-Port SRAM • Up to 71 User I/Os Reprogrammable Flash Technology • 130-nm, 7-Layer Metal 6 Copper , Flash-Based CMOS
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Original
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PDF
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130-nm,
128-Bit
MARKING 9AB
A3PN030Z
A3PN250Z
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Untitled
Abstract: No abstract text available
Text: IGLOO PLUS Handbook IGLOO PLUS Handbook Table of Contents Low-Power Flash Device Handbooks Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i Section I – IGLOO PLUS Datasheet IGLOO PLUS Low-Power Flash FPGAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
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Untitled
Abstract: No abstract text available
Text: v1.0 IGLOO PLUS Low-Power Flash FPGAs with Flash*Freeze Technology Features and Benefits High-Performance Routing Hierarchy Low Power Advanced I/O • • • • • 1.2 V or 1.5 V Core Voltage for Low Power Supports Single-Voltage System Operation 5 µW Power Consumption in Flash*Freeze Mode
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Original
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PDF
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actel date code
Abstract: No abstract text available
Text: Revision 8 ProASIC3 nano Flash FPGAs Features and Benefits Advanced I/Os Wide Range of Features • 10 k to 250 k System Gates • Up to 36 kbits of True Dual-Port SRAM • Up to 71 User I/Os Reprogrammable Flash Technology • 130-nm, 7-Layer Metal 6 Copper , Flash-Based CMOS
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