INTEL SERIES GATE ARRAY Search Results

INTEL SERIES GATE ARRAY Result Highlights (5)

Part	Manufacturer	Description
PQU650M-F-COVER	Murata Manufacturing Co Ltd	PQU650M Series - 3x5 Fan Cover Kit, RoHs Medical
DFE2016CKA-1R0M=P2	Murata Manufacturing Co Ltd	Fixed IND 1uH 1800mA NONAUTO
BLM15PX121BH1D	Murata Manufacturing Co Ltd	FB SMD 0402inch 120ohm POWRTRN
BLM15PX181SH1D	Murata Manufacturing Co Ltd	FB SMD 0402inch 180ohm POWRTRN
MGN1S1208MC-R7	Murata Manufacturing Co Ltd	DC-DC 1W SM 12-8V GAN

INTEL SERIES GATE ARRAY Datasheets Context Search

Catalog Datasheet	Type	Document Tags	PDF
M5C060-45 Abstract: M5C060 E 817 271046 5CO60 M5C060-55 Text: INTEL inteT CORP UP/PRPHLS 1 EE D I I Mfl2 t>175 □ Q7 E 5 EÖ □ T - H L - 1 3 - 1 /7 M 5CO60 600 GATE CHMOS H-SERIES ERASABLE PROGRAMMABLE LOGIC DEVICE H-EPLD Military High Performance Upgrade for Commonly Used 24-Pin PLDs Programmable Clock System with Two	OCR Scan	5CO60 24-Pin 24-Lead 5C060 D72S4M M5C060 00725M5 M5C060 M5C060-45 E 817 271046 M5C060-55	PDF
Robinson Nugent CATALOG Abstract: MC68461 SAB80286 WE32104 Z80000 IMST414 FGE2000 MCA2800ALS 82786 intel TC110G Text: T Circuit C o m p o n en ts Inc. r MicrofQ 3000 PGA Decoupling Capacitors Micro/Q 3000 ceramic capacitors are a family of very low inductance decoupling capacitors specifically designed to be through-hole mounted under pin grid arrays PGAs , PGA sockets, and	OCR Scan		PDF
sharp schematic Abstract: sharp display timing interface L296 Text: GATE ARRAYS AND CELL-BASED ICs SF-CAD ASIA ONLY The SF-CAD (Com puter-Aided Design) system is an IBM PC-compatible stand-alone gate array developm ent system. It integrates all the functions necessary for developing gate arrays form logic input to logic sim ulation. Based on SHARP'S "In-C ustom er Design Center" concept.	OCR Scan		PDF
LS 7475 Abstract: 7475 D flip-flop 7475 TRANSPARENT LATCH EP1210 FLIP FLOP 7475 5C121 74HC 74hc xor gate PIN CONFIGURATION 7475 TTL 7475 Text: intei 5C121 1200 GATE CHMOS H-SERIES ERASABLE PROGRAMMABLE LOGIC DEVICE l Advanced Architecture Features Including Programmable Output Polarity Active High/Low , Register By-Pass and Reset Controls • High Performance LSI Semi-Custom Logic Replacement for Gate Arrays and	OCR Scan	5C121 40-Lead EP1210 5C121 LS 7475 7475 D flip-flop 7475 TRANSPARENT LATCH EP1210 FLIP FLOP 7475 74HC 74hc xor gate PIN CONFIGURATION 7475 TTL 7475	PDF
Untitled Abstract: No abstract text available Text: in te l' M5C090 900 GATE CHMOS ERASABLE PROGRAMMABLE LOGIC DEVICE EPLD Military High Perform ance LSI Semicustom Logic Replacem ent fo r Low-End Gate Arrays TTL and 54HC SSI and MSI Logic Programmable Clock System with Tw o Synchronous Clocks as Well as	OCR Scan	M5C090	PDF
Untitled Abstract: No abstract text available Text: intei M5C060 600 GATE CHMOS ERASABLE PROGRAMMABLE LOGIC DEVICE EPLD Military High Performance LSI Semicustom Logic Replacement for Low-End Gate Arrays TTL and 54HC SSI and MSI Logic Programmable Clock System with Two Synchronous Clocks as Well as Asynchronous Clocking Option on All	OCR Scan	M5C060	PDF
IBM schematics Abstract: IBM PC AT schematics sharp schematic IBM PC schematics Text: GATE ARRAYS AND CELL-BASED ICs I SF-CAD A SIA ONLY The SF-CAD (Com puter-Aided Design) system is an IBM PC-compatible stand-alone gate array developm ent system. It integrates all the functions necessary for developing gate arrays except automatic layout from logic input to logic simulation. Based on SHARP'S "InCustom er Design Center" concept SF-CAD helps customers efficiently develop their gate arrays in-house.	OCR Scan		PDF
7475 d-flip flop Abstract: LS 7475 7475 D latch 7475 data latch altera EP1210 FLIP FLOP 7475 PIN CONFIGURATION 7475 programmer EPLD Register 7475 EP1210 Text: intei 5C121 1200 GATE CHMOS H-SERIES ERASABLE PROGRAMMABLE LOGIC DEVICE l Advanced Architecture Features Including Programmable Output Polarity Active High/Low , Register By-Pass and Reset Controls High Performance LSI Semi-Custom Logic Replacement for Gate Arrays and	OCR Scan	5C121 40-Lead EP1210 5C121 7475 d-flip flop LS 7475 7475 D latch 7475 data latch altera EP1210 FLIP FLOP 7475 PIN CONFIGURATION 7475 programmer EPLD Register 7475 EP1210	PDF
PLC88 Abstract: intel CMOS PLD intel PLD intel FPGA 29052 FX760 Text: int ! ÄO m iM ©! 0M F fô[iiflAT0®M ÌFX760 10 ns FLEXIogic FPGA WITH SRAM OPTION • High Performance FPGA (Field Programmable Gate Array — Deterministic 10 ns Pin-to-Pin Propagation Delays — 80 MHz System Clock Frequency Any CFB can be either 24V10 Logic or	OCR Scan	FX760 24V10 12-Bit 625or FX760 84-PIN PLC88 intel CMOS PLD intel PLD intel FPGA 29052	PDF
intel FPGA Abstract: FX730 intel PLD intel Series Gate Array IFX730 IC LM 317 Text: i n * ! O M F K iÆ Â ¥ D ® lM ÌFX730 10 ns FLEXIogic FPGA FAMILY WITH SRAM OPTION High Performance FPGA (Field Programmable Gate Array — Deterministic 10 ns Pin-to-Pin Propagation Delays — 80 MHz System Clock Frequency Any CFB Can Be Either 24V10 Logic or	OCR Scan	FX730 24V10 Configuratio467 intel FPGA intel PLD intel Series Gate Array IFX730 IC LM 317	PDF
Untitled Abstract: No abstract text available Text: Product Brief January 2002 ORCA OR3LxxxB Series Field-Programmable Gate Arrays Features • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ High-performance, cost-effective, 0.25 µm 5-level metal technology. 2.5 V internal supply voltage and 3.3 V I/O supply voltage for speed and compatibility.	Original	16-bit 208-Pin 240-Pin 352-Pin 432-Pin 680-Pin OR3L165B OR3L225B PN00-012FPGA PN99-053FPGA)	PDF
TRANSISTOR A30 Abstract: A30 TRANSISTOR Intel 8237A Text: GFI2370A GFI2370A GFI2370A DMA CONTROLLER GENERAL DESCRIPTION : THE GFI2370A IS COMPATIBLE IN FUNCTIONALITY WITH THE INTEL 8237A 4-CHANNEL PROGRAMMABLE DMA CONTROLLER. THE PERFORMANCE IS MUCH IMPROVED OVER THE STANDARD PART. FOR A DETAILED FUNCTIONAL DESCRIPTION, SEE THE INTEL DATA BOOK.	OCR Scan	GFI2370A GFI2370A LL7000 LSA2000 TRANSISTOR A30 A30 TRANSISTOR Intel 8237A	PDF
28F008SC Abstract: I960 hx 80960RP i960RP Text: E TECHNICAL PAPER Interfacing the Byte-Wide SmartVoltage FlashFile Memory Family to the Intel960 Microprocessor Family October 1996 Order Number: 297804-001 Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or	Original	Intel960® 80960JA/JF 32-Bit 80L960JA/JF 80960RP 80960HA/HD/HT 28F008SC I960 hx i960RP	PDF
LTC1307 Abstract: Flash Translation Layer XSR 28F160S5 F008 28F008S5 28F008SA 28F016S5 28F016SA 28F016SV 28F640J5 Text: E AP-647 APPLICATION NOTE 5 Volt Intel StrataFlash Memory Design Guide July 1999 Order Number: 292205-004 Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of	Original	AP-647 SCBA012A LTC1307 Flash Translation Layer XSR 28F160S5 F008 28F008S5 28F008SA 28F016S5 28F016SA 28F016SV 28F640J5	PDF

bld386 Abstract: Specification 386 Object Modules Format 482991-002 XLINK386 BLD-386 omf-386 OH386 OMF386 IC386 object module format 386 PROM386 Text: Analysis Of Object File Formats For Embedded Systems Minda Zhang, Ph.D Senior software engineer Intel Corporation June, 1995 1. Introduction An object file format is the lowest level file format for any platform. It is designed with the primary goal of providing formatted binaries of machine codes, initialized data and uninitialized data for an	Original	Intel386TM AP-713 bld386 Specification 386 Object Modules Format 482991-002 XLINK386 BLD-386 omf-386 OH386 OMF386 IC386 object module format 386 PROM386	PDF
Untitled Abstract: No abstract text available Text: in t e T 5C121 1200 GATE CHMOS H-SERIES ERASABLE PROGRAMMABLE LOGIC DEVICE Advanced Architecture Features Including Programmable Output Polarity Active High/Low , Register By-Pass and Reset Controls Programmable Clock System for Input Latches and Output Registers	OCR Scan	5C121 40-Lead	PDF
intel FPGA Abstract: intel PLD Text: int ! ÌFX8160 10 ns FLEXIogic FPGA WITH SRAM OPTION High Performance FPGA Field Programmable Gate Array — Deterministic 10 ns Pin-to-Pin Propagation Delays — 80 MHz System Clock Frequency Electrically Erasable 0.6y, ETOX* IV CHMOS FLASH Technology	OCR Scan	IFX8160 24V10 12-Bit intel FPGA intel PLD	PDF
Untitled Abstract: No abstract text available Text: Ä P Ä M g l D K 1 IF K 1 M 1 Ä T 0 ® M in te i ÌFX8160 10 ns FLEXIogic FPGA WITH SRAM OPTION High Performance FPGA Field Programmable Gate Array — Deterministic 10 ns Pin-to-Pin Propagation Delays — 80 MHz System Clock Frequency Electrically Erasable 0.6p, ETOX* IV	OCR Scan	FX8160 24V10	PDF
LUCENT 277 Abstract: ci 7495 intel FPGA CI LM 555 Text: Product Brief November 1999 ORCA OR3LxxxB Series Field-Programmable Gate Arrays Features • Abundant hierarchical routing resources based on routing two data nibbles and two control lines per set provide for faster place and route implementations and less routing delay.	Original	PN00-012FPGA PN99-053FPGA) LUCENT 277 ci 7495 intel FPGA CI LM 555	PDF
Untitled Abstract: No abstract text available Text: INTEL CORP MEMORY/PL] / böE D 4ß Sb l7 b GDflBDBfl 024 « I T L S A P m i M C B 0 M ( F [{ 3 R M ir 0 ® W In te l ) ÌFX8160 10 ns FLEXIogic FPGA WITH SRAM OPTION High Performance FPGA (Field Programmable Gate Array) — Deterministic 10 ns Pin-to-Pin	OCR Scan	FX8160 24V10	PDF
pcmcia flash card Abstract: AB-56 AP-662 28F008S5 28F008SA 28F016S5 28F016SA INTEL application notes Intel AP MB245 Text: E AP-662 APPLICATION NOTE Migrating from Series 2+ to Value Series 100 PC Cards  for Systems Using Basic 28F008SA Command Set Programming Model June 1998 Order Number: 292220-001 Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or	Original	AP-662 28F008SA AB-56 AP-622 pcmcia flash card AP-662 28F008S5 28F008SA 28F016S5 28F016SA INTEL application notes Intel AP MB245	PDF
flash memory vhdl code Abstract: speedwave Viewlogic 28F001BX 28F002BC 28F002BX 28F010 28F020 28F200BX vhdl code memory Text: COMPUTER-AIDED ENGINEERING TOOLS VIEWLOGIC SYSTEMS SpeedWave* • ■ ■ ■ ■ ■ ■ ■ ■ ■ Complete IEEE 1076 VHDL Complete interactive debugger Navigator for traversing the design hierarchy Context-sensitive help for ease of learning Imports EDIF netlists and	Original	28F010, 28F001BX, 28F020, 28F002BC, 28F002BL, 28F002BV, 28F002BX, 28F200BL, 28F200BV, 28F200BX, flash memory vhdl code speedwave Viewlogic 28F001BX 28F002BC 28F002BX 28F010 28F020 28F200BX vhdl code memory	PDF
telematics control unit Abstract: 8002-MC Text: CarCube Within XILINX’ and ACUNIA jointly offer the CarCube™. CarCube™ is a reference design for in-car multimedia infotainment systems. This reference design is built on XINGU technology which is based on Xilinx’ Spartan II FPGA and the ® Intel Xscale™ Micro-architecture.	Original	900nx B-3001, telematics control unit 8002-MC	PDF
NFX780-15 Abstract: KUFX780-10 KUFX780 intel FPGA tms 1035 128x10 intel PLD NFX780-10 FX780 PROTEUS-UPLC88 Text: in te i P R S O B M A I f f if ÌFX780 10 ns FLEXIogic FPGA WITH SRAM OPTION High Performance FPGA Field Programmable Gate Array — Deterministic 10 ns Pin-to-Pin Propagation Delays — 80 MHz System Clock Frequency Any CFB can be either 24V10 Logic or	OCR Scan	FX780 24V10 12-Bit VCC06) NFX780-15 KUFX780-10 KUFX780 intel FPGA tms 1035 128x10 intel PLD NFX780-10 PROTEUS-UPLC88	PDF

INTEL SERIES GATE ARRAY Search Results

INTEL SERIES GATE ARRAY Result Highlights (5)

INTEL SERIES GATE ARRAY Datasheets Context Search

M5C060-45

Robinson Nugent CATALOG

sharp schematic

LS 7475

Untitled

Untitled

IBM schematics

7475 d-flip flop

PLC88

intel FPGA

Untitled

TRANSISTOR A30

28F008SC

LTC1307

bld386

Untitled

intel FPGA

Untitled

LUCENT 277

Untitled

pcmcia flash card

flash memory vhdl code

telematics control unit

NFX780-15