INTEL 80960 PIPELINE ARCHITECTURE Search Results

INTEL 80960 PIPELINE ARCHITECTURE Result Highlights (5)

Part	Manufacturer	Description
29818APC	Rochester Electronics LLC	AM29818A - Pipeline Register
29520ALM/B	Rochester Electronics LLC	AM29520 - Multilevel Pipeline Register
EN80C188XL-20	Rochester Electronics LLC	80C188XL - MPU Intel 186 CISC 16-Bit
MG80960MC-25/B	Rochester Electronics LLC	80960MC - 32-Bit Microprocessor With Floating Point Unit and MMU
MQ80960MC-25	Rochester Electronics LLC	80960MC - 32-Bit Microprocessor With Floating Point Unit and MMU

INTEL 80960 PIPELINE ARCHITECTURE Datasheets Context Search

Catalog Datasheet	Type	Document Tags	PDF
80960MC Abstract: INTEL 80960 pipeline architecture M82965 80960 Text: Introduction to the 80960 Architecture 2 CHAPTER 2 INTRODUCTION TO THE 80960 ARCHITECTURE This chapter provides an overview of the architecture on which the 80960MC processor is based. A NEW 32-BIT ARCHITECTURE FROM INTEL The 80960MC processor is the military-grade member of a new family of processors from	OCR Scan	80960MC 32-BIT INTEL 80960 pipeline architecture M82965 80960	PDF
M82965 Abstract: No abstract text available Text: 80960MC PRODUCT OVERVIEW This chapter provides an overview o f the architecture o f the 80960M C processor. The 80960M C processor is the m ilitary-grade m em ber o f a new fam ily o f processors from Intel. This processor family is based on a new 32-bit architecture called the 80960 architecture. The	OCR Scan	80960MC 80960M 32-bit M82965	PDF
a6059 Abstract: a6060 pin diagram of intel dual core processor semiconductor A6060 A6060-01 32-bit microprocessor architecture 80960Rm addressing modes of dual core processor clock generator in dual core processor 80960JT Text: Introduction 1.1 1 Intel’s i960 RM/RN I/O Processor The i960 RM/RN I/O processor integrates a high-performance 80960 “core” into a Peripheral Components Interconnect PCI functionality. This integrated processor addresses the needs of intelligent I/O applications and helps reduce intelligent I/O system costs. As indicated in	Original		PDF
branch conditional unconditional instruction Abstract: 80960CF Intel 960 Text: 80960CF-40, -33, -25, -16 1.0 PURPOSE 2.0 This document provides electrical characteristics of Intel's ¡960 CF embedded microprocessor. For functional descriptions consult the /'960® Cx Micro processor User’s Manual 270710 . To obtain data sheet updates and errata, contact Intel at any of the	OCR Scan	80960CF-40, 80960CF 80960CA 80960HA/HD/HT. 80960Cx branch conditional unconditional instruction Intel 960	PDF
Date Code Formats intel Abstract: 80960 Programmer Reference manual 80960MC 80960 Reference Manual Text: Guide to this Manual 1 CHAPTER 1 GUIDE TO THIS MANUAL This chapter describes the organization o f this m anual, the contents o f each chapter, and term inology used in the manual. It also outlines the chapters o f the manual that are o f m ost interest to applications program m ers, com piler designers, and designers of operating-system	OCR Scan	80960MC Date Code Formats intel 80960 Programmer Reference manual 80960 Reference Manual	PDF
Untitled Abstract: No abstract text available Text: 3.3 V 80960JA/JF 1.0 PURPOSE This docum ent contains inform ation for the 80960JA/JF microprocessor, including electrical characteristics and package pinout information. Detailed functional descriptions — other than para m etric perform ance — are published in the i96 P Jx	OCR Scan	80960JA/JF 80960JA/JF 80960Jx" 80960JA 80960JF 80960JD 80960JD 80960Jx	PDF
Untitled Abstract: No abstract text available Text: 80960JD 1.0 PURPOSE This document contains advance inform ation for the 80960JD microprocessor, including electrical characteristics and package pinout information. Detailed functional descriptions — other than param etric perform ance — are published in the	OCR Scan	80960JD 80960JD 80960Jx" 80960JA 80960JF 80960J 80L960JA 80960JA 80L960JF 80960JF	PDF
i486 sx Abstract: 80960CX 80960JF 80960RD 80960RP 272736 272918 INTEL386 pipeline architecture Text: Intel i960® RX I/O Processor at 3.3 Volts Datasheet • 33 MHz, 3.3 Volt Version 80960RP 33/3.3 • 66 MHz, 3.3 Volt Version (80960RD 66/3.3) - Clock Doubled 80960JF Core • Complies with PCI Local Bus Specification, Revision 2.1 • 5 Volt PCI Signalling Environment	Original	80960RP 80960RD 80960JF 32-Bit 32-Bit i486 sx 80960CX 272736 272918 INTEL386 pipeline architecture	PDF
Intel i960 VH Embedded-PCI Processor Provides Integrated Memory Control and PCI Bus Interface Abstract: No abstract text available Text: i960 VH Embedded-PCI Processor Advance Information Datasheet Product Features • High Performance 80960JT Core — Sustained One Instruction/Clock Execution — 16 Kbyte Two-Way Set-Associative Instruction Cache — 4 Kbyte Direct-M apped Data Cache — Sixteen 32-Bit Global Registers	OCR Scan	80960JT 32-Bit Intel i960 VH Embedded-PCI Processor Provides Integrated Memory Control and PCI Bus Interface	PDF
80960Cx Abstract: PCI80960 80960JF 80960RP i960RP Text: Intel i960® RP I/O Processor Datasheet • 33 MHz, 5 Volt Version 80960RP 33/5.0 • Complies with PCI Local Bus Specification, Revision 2.1 Product Features • ■ ■ ■ ■ High Performance 80960JF Core —Sustained One Instruction/Clock Execution	Original	80960RP 80960JF 32-Bit 32-Bit 64-Byte Forwar80960RP-series 80960RP 80960Cx PCI80960 i960RP	PDF
8096 processor architecture Abstract: No abstract text available Text: intei 1.0 8 0 9 6 0 H A/H D / H T This docum ent provides a preview of Intel’s 80960Hx embedded superscalar microprocessors. Future revisions of this docum ent will provide targeted electrical characteristics. Detailed descriptions for functional topics — other than param etric perfor	OCR Scan	80960Hx 80960H 80960Cx 8096 processor architecture	PDF
80960JT Abstract: 80960VH AD10 MA11 273179 Text: i960 VH Embedded-PCI Processor Advance Information Datasheet Product Features • ■ ■ ■ High Performance 80960JT Core — Sustained One Instruction/Clock Execution — 16 Kbyte Two-Way Set-Associative Instruction Cache — 4 Kbyte Direct-Mapped Data Cache	Original	80960JT 32-Bit 32-Bit 80960VH AD10 MA11 273179	PDF
80960JT Abstract: 80960VH AD10 MA11 Text: i960 VH Embedded-PCI Processor Advance Information Datasheet Product Features • ■ ■ ■ High Performance 80960JT Core — Sustained One Instruction/Clock Execution — 16 Kbyte Two-Way Set-Associative Instruction Cache — 4 Kbyte Direct-Mapped Data Cache	Original	80960JT 32-Bit 32-Bit 80960VH AD10 MA11	PDF
A10 bga Abstract: intel flash memory W18 80960JT 80960VH AD10 MA11 Text: i960 VH Embedded-PCI Processor Preliminary Datasheet Product Features • ■ ■ ■ High Performance 80960JT Core — Sustained One Instruction/Clock Execution — 16 Kbyte Two-Way Set-Associative Instruction Cache — 4 Kbyte Direct-Mapped Data Cache	Original	80960JT 32-Bit 32-Bit 1710H A10 bga intel flash memory W18 80960VH AD10 MA11	PDF

80960VH Abstract: INTEL DX2 80960JT AD10 MA11 cc5r Text: i960 VH Embedded-PCI Processor Preliminary Datasheet Product Features • ■ ■ ■ High Performance 80960JT Core — Sustained One Instruction/Clock Execution — 16 Kbyte Two-Way Set-Associative Instruction Cache — 4 Kbyte Direct-Mapped Data Cache	Original	80960JT 32-Bit 32-Bit 1710H 80960VH INTEL DX2 AD10 MA11 cc5r	PDF
Untitled Abstract: No abstract text available Text: ADVANCE INFORMATION ¡960 RP/RD I/O PROCESSOR AT 3.3 VOLTS 33 MHz, 3.3 Volt Version 80960RP 33/3.3 66 MHz, 3.3 Volt Version (80960RD 66/3.3) - Clock Doubled 80960J F Core • Complies with PCI Local Bus Specification Revision 2.1 • 5 Volt P C I Signalling Environment	OCR Scan	80960RP 80960RD 80960J 80960JF 32-Bit 64-Byhe	PDF
272737 Abstract: 80960JF 80960RD 80960RP AD10 AD11 MA11 27248 Text: ADVANCE INFORMATION i960 RP/RD I/O PROCESSOR AT 3.3 VOLTS • • • • 33 MHz, 3.3 Volt Version 80960RP 33/3.3 66 MHz, 3.3 Volt Version (80960RD 66/3.3) - Clock Doubled 80960JF Core Complies with PCI Local Bus Specification Revision 2.1 5 Volt PCI Signalling Environment	Original	80960RP 80960RD 80960JF 32-Bit 32-Bit 272737 AD10 AD11 MA11 27248	PDF
Untitled Abstract: No abstract text available Text: Ä I D W M C S Ö M F @ [^ M Ä ?D [K 1 ir tU October 1989 3 80960CA Product Overview 32-Bit High-Performance Embedded Processor with On-Chip DMA Controller, Interrupt Controller, High-Speed Bus Unit, Instruction and Register Caches Order Number: 270669-001	OCR Scan	80960CA 32-Bit 80960CA 80960CAâ 00000000H 000003FFH.	PDF
chromerics Abstract: OV26 80960JF 80960RP AD10 AD11 MA11 272736 27248 i960RP Text: ADVANCE INFORMATION i960 RP I/O PROCESSOR • 33 MHz, 5.0 Volt Version 80960RP 33/5.0 • Complies with PCI Local Bus Specification Revision 2.1 • High Performance 80960JF Core ■ ■ ■ ■ ■ DMA Controller — Sustained One Instruction/Clock Execution	Original	80960RP 80960JF 32-Bit 32-Bit 64-Byte ForTOV27 chromerics OV26 AD10 AD11 MA11 272736 27248 i960RP	PDF
80960MC Abstract: processor cross reference INTEL 80960 pipeline architecture Text: Introduction to the 80960MC Microprocessor CHAPTER 1 INTRODUCTION TO THE 80960MC MICROPROCESSOR The 80960MC is the military version of the 80960 family, designed especially for high reliability embedded applications. At an operating frequency of 20 MHz, this high performance processor can	OCR Scan	80960MC processor cross reference INTEL 80960 pipeline architecture	PDF
272737 Abstract: 80960JF Text: IP[n3 [ [!J©T [PGiEWOG in te i 80960RP INTELLIGENT I/O MICROPROCESSOR • ■ PCI-to-PCI BRIDGE UNIT HIGH PERFORMANCE 80960JF CORE — Primary and Secondary PCI Interfaces — Sustained One Instruction/Clock — Two 64-Byte Posting Buffers Execution — Supports Delayed and Posted	OCR Scan	80960RP 80960JF 64-Byte 32-Bit 80960RP 272737	PDF
80960SA Abstract: 80960SB Text: Introduction to ¡960 Architecture 2 CH A PTER 2 IN TR O D U C T IO N TO i960™ A R C H ITE C TU R E This chapter provides an overview of the architecture on which the 80960 series o f processors is based. AN EMBEDDED 32-BIT ARCHITECTURE FROM INTEL The 80960SA/SB processor marks the continuation o f the i960 architecture series — an	OCR Scan	32-BIT 80960SA/SB 16-bit 80960SA 80960SB	PDF
diode byt 45 Abstract: 80960RP 80960JF AD10 MA11 272736 Text: A ADVANCE INFORMATION 80960RP THE IQ SERIES INTELLIGENT I/O MICROPROCESSOR • ■ ■ ■ ■ • Complies with PCI Local Bus Specification Revision 2.1 High Performance 80960JF Core ■ DMA Controller — Sustained One Instruction/Clock — Three Independent Channels	Original	80960RP 80960JF 32-Bit 64-Bit 32-Bit 80960RP 352-Lead diode byt 45 AD10 MA11 272736	PDF
Embedded Applications Handbook 270646 Abstract: intel Multibus i handbook 230843 embedded controller handbook Mohawk 80960MC 80960 1989 intel I860 processor 270646 multibus II architecture specification Text: 80960MC Hardware Designer’s Reference Manual June, 1989 Order Number: 271079-002 intei LITERATURE T o o rd er Intel Literature or obtain literature pricing inform ation in the U .S. and C anad a call or w rite Intel Literature Sales. In Europe and other international locations, please contact your local sales office or	OCR Scan	80960MC Embedded Applications Handbook 270646 intel Multibus i handbook 230843 embedded controller handbook Mohawk 80960 1989 intel I860 processor 270646 multibus II architecture specification	PDF

INTEL 80960 PIPELINE ARCHITECTURE Search Results

INTEL 80960 PIPELINE ARCHITECTURE Result Highlights (5)

INTEL 80960 PIPELINE ARCHITECTURE Datasheets Context Search

80960MC

M82965

a6059

branch conditional unconditional instruction

Date Code Formats intel

Untitled

Untitled

i486 sx

Intel i960 VH Embedded-PCI Processor Provides Integrated Memory Control and PCI Bus Interface

80960Cx

8096 processor architecture

80960JT

80960JT

A10 bga

80960VH

Untitled

272737

Untitled

chromerics

80960MC

272737

80960SA

diode byt 45

Embedded Applications Handbook 270646