Please enter a valid full or partial manufacturer part number with a minimum of 3 letters or numbers

    INFINIBAND PHYSICAL MEDIUM ATTACHMENT Search Results

    INFINIBAND PHYSICAL MEDIUM ATTACHMENT Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    CS-SAS2MUKPTR-000.5 Amphenol Cables on Demand Amphenol CS-SAS2MUKPTR-000.5 External Mini-SAS Cable (Pull-Tab) - 4x Mini-SAS (SFF-8088) to 4x Mini-SAS (SFF-8088) 0.5m Datasheet
    CS-SAS2MUKPTR-002 Amphenol Cables on Demand Amphenol CS-SAS2MUKPTR-002 External Mini-SAS Cable (Pull-Tab) - 4x Mini-SAS (SFF-8088) to 4x Mini-SAS (SFF-8088) 2m Datasheet
    CS-SAS2MUKPTR-006 Amphenol Cables on Demand Amphenol CS-SAS2MUKPTR-006 External Mini-SAS Cable (Pull-Tab) - 4x Mini-SAS (SFF-8088) to 4x Mini-SAS (SFF-8088) 6m Datasheet
    CS-SASMINTOHD-002 Amphenol Cables on Demand Amphenol CS-SASMINTOHD-002 2m (6.6') External 4x Mini-SAS to HD Mini-SAS Cable - 4x Mini-SAS HD (SFF-8644) to 4x Mini-SAS 26-pin (SFF-8088) Passive Copper Cable [28 AWG] - 6G SAS 2.1 / iPass+™ HD Datasheet
    CS-SASMINTOHD-003 Amphenol Cables on Demand Amphenol CS-SASMINTOHD-003 3m (9.8') External 4x Mini-SAS to HD Mini-SAS Cable - 4x Mini-SAS HD (SFF-8644) to 4x Mini-SAS 26-pin (SFF-8088) Passive Copper Cable [28 AWG] - 6G SAS 2.1 / iPass+™ HD Datasheet

    INFINIBAND PHYSICAL MEDIUM ATTACHMENT Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    infiniband Physical Medium Attachment

    Abstract: fiber patch panels Teradyne connector P802 10G SFP msa parallel transceiver 1998 85m300 Serial RapidIO Infiniband simplex 4010 shielded twisted pair Fibre channel driver
    Text: White Paper: Virtex-II Series R WP157 v1.0 March 15, 2002 Usage Models for Multi-Gigabit Serial Transceivers By: Scott Irwin This document provides an overview of the various usage models for high-speed, point-to-point, serial transceiver technology. While not intending to


    Original     		PDF WP157 WP151-800-255-7778 VSR-4-04 OC-192 infiniband Physical Medium Attachment fiber patch panels Teradyne connector P802 10G SFP msa parallel transceiver 1998 85m300 Serial RapidIO Infiniband simplex 4010 shielded twisted pair Fibre channel driver

    infiniband Physical Medium Attachment

    Abstract: CX27201 TLK3101 VSC7123 VSC7216-01 XC2VP20 XC2VP30 XC2VP40 XC2VP70 SIGNAL PATH DESIGNER
    Text: White Paper: Virtex-II Pro Family R WP160 v1.1 October 22, 2002 Emulating External SERDES Devices with Embedded RocketIO Transceivers By: Matt DiPaolo The Virtex-II Pro Platform FPGA provides an attractive single-chip solution to serial transceiver design problems that previously required multiple


    Original     		PDF WP160 VSC7123, VSC7216-01, TLK3101, CX27201. infiniband Physical Medium Attachment CX27201 TLK3101 VSC7123 VSC7216-01 XC2VP20 XC2VP30 XC2VP40 XC2VP70 SIGNAL PATH DESIGNER

    64B66B

    Abstract: 8B10B in serial communication fiber TRANSCEIVER CIRCUIT DIAGRAM rs232 1000H OC-768 VME64 8B10B asic 8B10B ansi encoder
    Text: White Paper The Evolution of High-Speed Transceiver Technology Introduction The Internet revolution has led to a massive increase in data traffic. This trend is set to continue; over the next few years and it is likely that 95% of all communication traffic will shift to data. The need to support high bandwidth


    Original     		PDF OC-48 OC-192 10Gbps) OC-768 40Gbps) 64B66B 8B10B in serial communication fiber TRANSCEIVER CIRCUIT DIAGRAM rs232 1000H VME64 8B10B asic 8B10B ansi encoder

    LXT35401

    Abstract: infiniband Physical Medium Attachment
    Text: product brief Intel LXT35401 10Gbps XAUI-to-Quad 3.2Gbps Transceiver Product Description The Intel® LXT35401 is a 4-channel re-timer for optical module, backplane and repeater applications. Integrated re-timing and de-skew functions simplify design trade-offs required to


    Original     		PDF LXT35401 10Gbps LXT35401 10GBASE-LX4 USA/0302/5K/MGS/DC infiniband Physical Medium Attachment

    X0838

    Abstract: X0910 MICRO CHIP X0848 Oscillator CQE 3RW29 08D0 WQ epson tx 121 circuit diagram vl15p 16K4 infiniband PHY
    Text: IBM PCI-X to InfiniBand Host Channel Adapter Datasheet Product Level 3.0 October 14, 2002  Copyright and Disclaimer  Copyright International Business Machines Corporation 2002 All Rights Reserved Printed in the United0l States of America October 2002.


    Original     		PDF 64-byte 32-bits X0838 X0910 MICRO CHIP X0848 Oscillator CQE 3RW29 08D0 WQ epson tx 121 circuit diagram vl15p 16K4 infiniband PHY

    LXT11001

    Abstract: No abstract text available
    Text: product brief Intel LXT11001 10Gbps Ethernet XAUI-to-XGMII Transceiver Device Product Description As the number of high-speed serial applications increases, the need for efficiencies in terms of power, layout options, and jitter budget become extremely important. The Intel® LXT11001 is an


    Original     		PDF LXT11001 10Gbps LXT11001 USA/0302/5K/MGS/DC

    k2872

    Abstract: SSTL-18 "programmable on-chip termination"
    Text: Using High-Speed Transceiver Blocks in Stratix GX Devices November 2002 , ver. 1.0 Introduction Application Note 237 Applications involving backplane and chip-to-chip architectures have become increasingly complex and, therefore, operate at higher data rates.


    Original     		PDF

    10G Ethernet PHy

    Abstract: STM-64 infiniband Physical Medium Attachment 0C-48 LVPECL XGC1120
    Text: New RocketPHY Transceiver Family Debuts at 10 Gbps A new family of 10 Gbps serial I/O transceivers dramatically cuts costs in light-speed applications. These transceivers make it possible to create unique optical connectivity designs. by Robert Bielby Senior Director, Strategic Solutions Marketing


    Original     		PDF OC-192 10G Ethernet PHy STM-64 infiniband Physical Medium Attachment 0C-48 LVPECL XGC1120

    "programmable on-chip termination"

    Abstract: MDIO clause 22 lazer diode LXT11001 LXT35401 10G BERT 10G serdes bert lazer intel xenpak
    Text: product brief Intel LXT35401 10Gbps XAUI-to-Quad 3.2G Transceiver Product Description The Intel® LXT35401 is a 4-channel re-timer for optical module, backplane and repeater applications. Integrated re-timing and de-skew functions simplify design trade-offs required to


    Original     		PDF LXT35401 10Gbps LXT35401 10GBASE-LX4 USA/0102/5K/MGS/DC "programmable on-chip termination" MDIO clause 22 lazer diode LXT11001 10G BERT 10G serdes bert lazer intel xenpak

    N305

    Abstract: No abstract text available
    Text: V23818-N305-L57 * Small Form Factor Multimode 850 nm 2.5 Gbit/s OC-48 2x5 Transceiver with LC Connector Preliminary Dimensions in mm [inches] a) recommended bezel position shown design with collar V23 818 -N3 05-L 57 FEATURES • Small Form Factor transceiver


    Original     		PDF V23818-N305-L57( OC-48 RJ-45 UL-94 D-13623, N305

    Optical SAS QSFP

    Abstract: CEI-6G-LR 28G-SR QSFP 32G CEI-11G QSFP QSFP CONNECTOR QSFP 25G ibis sata interlaken
    Text: White Paper Extending Transceiver Leadership at 28 nm High-speed serial protocols with increased data rates and expanded capabilities are addressing the demand for more network bandwidth. Efficiently supporting the subsequent increase in system bandwidth by attaining higher data


    Original     		PDF 28-Gbps Optical SAS QSFP CEI-6G-LR 28G-SR QSFP 32G CEI-11G QSFP QSFP CONNECTOR QSFP 25G ibis sata interlaken

    Untitled

    Abstract: No abstract text available
    Text: V23818-N305-L57 * Small Form Factor Multimode 850 nm 2.5 Gbit/s OC-48 2x5 Transceiver with LC Connector Preliminary Dimensions in mm [inches] V23 818 -N3 05-L 57 *) Ordering Information Input Output Signal detect Voltage Part number AC AC 3.3 V V23818-N305-L57


    Original     		PDF V23818-N305-L57( OC-48 V23818-N305-L57 RJ-45 D-13623,

    infiniband Physical Medium Attachment

    Abstract: "toan nguyen" 200MHZ P802 circuit diagram digital clocks Serial RapidIO Infiniband FPGA SoC, Chip, telecom fpga da altera altera 48 fpga 1gbps serdes
    Text: Architecture and Methodology of a SoPC with 3.25Gbps CDR based Serdes and 1Gbps Dynamic Phase Alignment Ramanand Venkata, Wilson Wong, Tina Tran, Vinson Chan, Tim Hoang, Henry Lui, Binh Ton, Sergey Shumurayev, Chong Lee, Shoujun Wang, Huy Ngo, Malik Kabani, Victor Maruri, Tin Lai, Tam Nguyen, Arch


    Original     		PDF 25Gbps 125Gbps 622megabits infiniband Physical Medium Attachment "toan nguyen" 200MHZ P802 circuit diagram digital clocks Serial RapidIO Infiniband FPGA SoC, Chip, telecom fpga da altera altera 48 fpga 1gbps serdes

    Serial RapidIO Infiniband

    Abstract: k307 K284
    Text: 2. Stratix GX Transceivers SGX51002-1.1 Transceiver Blocks Stratix GX devices incorporate dedicated embedded circuitry on the right side of the device, which contains up to 20 high-speed 3.1875-Gbps serial transceiver channels. Each Stratix GX transceiver block contains


    Original     		PDF SGX51002-1 1875-Gbps Serial RapidIO Infiniband k307 K284

    K241

    Abstract: K-241 gxb tx_coreclk P802
    Text: 5. XAUI Mode SGX52005-1.2 Introduction The 10 Gigabit Attachment Unit Interface XAUI is an optional, self-managed interface that can be inserted between the reconciliation sublayer and the PHY layer to transparently extend the physical reach of the 10 Gigabit Media Independent Interface (XGMII).


    Original     		PDF SGX52005-1 K241 K-241 gxb tx_coreclk P802

    k241

    Abstract: 1000BASE-X h17c 8HBC
    Text: 6. GIGE Mode SGX52006-1.2 Introduction The Gigabit Ethernet GIGE mode in Stratix GX devices supports a subset of the IEEE GIGE standard. Stratix GX devices have Physical Coding Sub-layer (PCS) functions and Physical Medium Attachment (PMA) functions as Hard Intellectual Property (IP).


    Original     		PDF SGX52006-1 8B/10B 10-bit k241 1000BASE-X h17c 8HBC

    SSTL-18

    Abstract: No abstract text available
    Text: Stratix GX November 2002, ver. 1.0 Introduction FPGA Family Data Sheet Preliminary Information The StratixTM GX family of devices is Altera’s second FPGA family to combine high-speed serial transceivers with a scalable, high-performance logic array. Stratix GX devices include 4 to 20 high-speed transceiver


    Original     		PDF

    circuit diagram of full subtractor circuit

    Abstract: "Fast Cycle RAM" Serial RapidIO Infiniband logic diagram to setup adder and subtractor 32 bit carry select adder code HP lvds connector 40 pin to 30 pin to 7 pin infiniband Physical Medium Attachment SSTL-18 transistor on 4436
    Text: Stratix GX March 2003, ver. 1.2 Introduction FPGA Family Data Sheet Preliminary Information The StratixTM GX family of devices is Altera’s second FPGA family to combine high-speed serial transceivers with a scalable, high-performance logic array. Stratix GX devices include 4 to 20 high-speed transceiver


    Original     		PDF

    SY 351/6

    Abstract: HP8656B service manual PWB 826 service manual PS 224 CITS25 DXSN2112 pj 939 PS-224 2 X 2 DUAL CROSSPOINT SWITCH amcc 10G palce programming algorithm
    Text: SERDES Handbook April 2003 Dear Valued Customer, Lattice Semiconductor is pleased to provide you this second edition of our SERDES Handbook. Since offering the initial version last year, we have introduced several new products based on our superior sysHSI technology:


    Original     		PDF ORT42G5 ORSO82G5 ORT82G5 ORSO42G5 1-800-LATTICE B0039 SY 351/6 HP8656B service manual PWB 826 service manual PS 224 CITS25 DXSN2112 pj 939 PS-224 2 X 2 DUAL CROSSPOINT SWITCH amcc 10G palce programming algorithm

    Untitled

    Abstract: No abstract text available
    Text: Speedster22i SerDes User Guide UG028 – May 21, 2013 UG028, May 21, 2013 1 Table of Contents Table of Contents . 2 Table of Figures . 5


    Original     		PDF Speedster22i UG028 UG028,

    ifr 4000 pcb circuit diagrams

    Abstract: hd-sdi pcb layout M21260 14305H 212xx-SWG-001 M21262 mf10 pcb layout mindspeed 424M HD-SDI over sdh
    Text: M21262 CDR/Reclocker with 4:1 Input Multiplexer The M21262 is a CDR/reclocker with 4:1 input multiplexer for telecom, datacom, and HD/SD video applications. Each output channel has an independent multi-rate CDR capable of operating at data rates between 42 Mbps and 3.2 Gbps.


    Original     		PDF M21262 M21262 21262-DSH-001-C ifr 4000 pcb circuit diagrams hd-sdi pcb layout M21260 14305H 212xx-SWG-001 mf10 pcb layout mindspeed 424M HD-SDI over sdh

    manual FW82801BA motherboard

    Abstract: intel chipset 845 motherboard repair circuit Intel 815 FW82815 motherboard review INTEL FW82801BA motherboard INTEL FW82801BA microtek inverter service manual National SG 250w audio amplifier circuit diagram lcd power board schematic hp 1502 rg82855gme Msi 533 845gv Motherboard
    Text: NOTE: PLEASE ADJUST SPINE TO PROPER WIDTH Europe Intel Corporation UK Ltd. Pipers Way Swindon Wiltshire SN3 1RJ UK Phone: England (44) 1793 403 000 France (33) 1 4694 7171 Germany (49) 89 99143 0 Italy (39) 02 575 441 Israel (972) 2 589 7111 Netherlands (31) 20 659 1800


    Original     		PDF USA/2004/10K/MD/HP manual FW82801BA motherboard intel chipset 845 motherboard repair circuit Intel 815 FW82815 motherboard review INTEL FW82801BA motherboard INTEL FW82801BA microtek inverter service manual National SG 250w audio amplifier circuit diagram lcd power board schematic hp 1502 rg82855gme Msi 533 845gv Motherboard

    circuit diagram of wifi wireless router

    Abstract: Apple Authentication coprocessor building own and cheap walkie-talkie smart card atm hack StrataXGS Broadcom baseband processor HP COMPAQ MOTHERBOARD CIRCUIT diagram Linksys gateway Broadcom 802.11 application note AUTOMATIC ROOM LIGHT CONTROLLER with visitor counter
    Text: Architecting Next-Generation Networks Produced Exclusively for Broadcom by Table of Contents Chapter 1: Introduction .1 Why Your Network Isn’t Good


    Original     		PDF

    RTL code for ethernet

    Abstract: transistor h5c verilog code of prbs pattern generator barrel shifter block diagram free verilog code of prbs pattern generator verilog code for 10 gb ethernet SGX52001-1 SGX52005-1
    Text: Section I. Stratix GX Transceiver User Guide This section provides information on the configuration modes for Stratix GX devices. It also includes information on testing, Stratix GX port and parameter information, and pin constraint information. This section includes the following chapters:


    Original     		PDF