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    IEEE SINGLE PRECISION FLOATING POINT MULTIPLIER Search Results

    IEEE SINGLE PRECISION FLOATING POINT MULTIPLIER Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    TMPM4GQF15FG Toshiba Electronic Devices & Storage Corporation Arm Cortex-M4 processor with FPU Core Based Microcontroller/32bit/P-LQFP144-2020-0.50-002 Visit Toshiba Electronic Devices & Storage Corporation
    TMPM4GRF20FG Toshiba Electronic Devices & Storage Corporation Arm Cortex-M4 processor with FPU Core Based Microcontroller/32bit/P-LQFP176-2020-0.40-002 Visit Toshiba Electronic Devices & Storage Corporation
    TMPM4KMFWAFG Toshiba Electronic Devices & Storage Corporation Arm Cortex-M4 processor with FPU Core Based Microcontroller/32bit/P-LQFP80-1212-0.50-003 Visit Toshiba Electronic Devices & Storage Corporation
    TMPM4MMFWAFG Toshiba Electronic Devices & Storage Corporation Arm Cortex-M4 processor with FPU Core Based Microcontroller/32bit/P-LQFP80-1212-0.50-003 Visit Toshiba Electronic Devices & Storage Corporation
    TMPM4NQF10FG Toshiba Electronic Devices & Storage Corporation Arm Cortex-M4 processor with FPU Core Based Microcontroller/32bit/P-LQFP144-2020-0.50-002 Visit Toshiba Electronic Devices & Storage Corporation

    IEEE SINGLE PRECISION FLOATING POINT MULTIPLIER Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    AN701

    Abstract: 3F80 EXCESS-127
    Text: Philips Semiconductors Application note SP floating point math with XA AN701 Author: Santanu Roy, MCO Applications Group, Sunnyvale, California IEEE SINGLE PRECISION FLOATING POINT ARITHMETIC WITH XA SIGN 1-bit This application note is intended to implement Single Precision


    Original     		PDF AN701 0xff000000) 0x00ff0000) 0x0000ff00) 0x000000ff; AN701 3F80 EXCESS-127

    Untitled

    Abstract: No abstract text available
    Text: SHARC Embedded Processor ADSP-21261/ADSP-21262/ADSP-21266 SUMMARY Single-instruction multiple-data SIMD computational architecture—two 32-bit IEEE floating-point/32-bit fixed-point/ 40-bit extended precision floating-point computational units, each with a multiplier, ALU, shifter, and register file


    Original     		PDF ADSP-21261/ADSP-21262/ADSP-21266 32-bit floating-point/32-bit 40-bit BC-136 ST-144

    ADSP-21065L

    Abstract: No abstract text available
    Text: & 180 5,& 250$76 Figure C-0. Table C-0. Listing C-0. The processor supports several numeric formats: • IEEE Standard 754/854, 32-bit, single-precision floating-point format. • An extended-precision version of the 32-bit, single-precision floating-point format that has eight additional bits in the mantissa (40


    Original     		PDF 32-bit, ADSP-21065L 24-bit 64-bit 80-bit ADSP-21065L

    ADSP-21060 reference manual

    Abstract: ADSP-21060 21060 hardware reference ADSP21000 ADSP-21000 ADSP-21060L ADSP-21061 ADSP-21062 21060lkb160 ADSP 21 XXX Sharc processor
    Text: a ADSP-2106x SHARC DSP Microcomputer Family ADSP-21060/ADSP-21060L IEEE JTAG Standard 1149.1 Test Access Port and On-Chip Emulation 240-Lead Thermally Enhanced MQFP Package 225 PBGA Package 32-Bit Single-Precision and 40-Bit Extended-Precision IEEE Floating-Point Data Formats or 32-Bit FixedPoint Data Format


    Original     		PDF ADSP-2106x ADSP-21060/ADSP-21060L 240-Lead 32-Bit 40-Bit Parallel10) ADSP-21060KS-133 ADSP-21060KS-160 ADSP-21060 reference manual ADSP-21060 21060 hardware reference ADSP21000 ADSP-21000 ADSP-21060L ADSP-21061 ADSP-21062 21060lkb160 ADSP 21 XXX Sharc processor

    ADSP-21060 reference manual

    Abstract: ADSP-21060 ADSP21060 ADSP21000 ADSP-21000 ADSP-21060L ADSP-21061 ADSP-21062 Tck12
    Text: a ADSP-2106x SHARC DSP Microcomputer Family ADSP-21060/ADSP-21060L IEEE JTAG Standard 1149.1 Test Access Port and On-Chip Emulation 240-Lead Thermally Enhanced MQFP Package 225 PBGA Package 32-Bit Single-Precision and 40-Bit Extended-Precision IEEE Floating-Point Data Formats or 32-Bit FixedPoint Data Format


    Original     		PDF ADSP-2106x ADSP-21060/ADSP-21060L 240-Lead 32-Bit 40-Bit Parallel10) ADSP-21060KS-133 ADSP-21060KS-160 ADSP-21060 reference manual ADSP-21060 ADSP21060 ADSP21000 ADSP-21000 ADSP-21060L ADSP-21061 ADSP-21062 Tck12

    ADSP-21060 simulator program download

    Abstract: ADSP-21060 reference manual ADSP-21060 SIMULATOR 4...20 mA ADSP21060 DESIGN AND IMPLEMENTATION 16-BIT BARREL SHIFTER ADSP21000 ADSP-21000 ADSP-21060L ADSP-21061
    Text: a ADSP-2106x SHARC DSP Microcomputer Family ADSP-21060/ADSP-21060L IEEE JTAG Standard 1149.1 Test Access Port and On-Chip Emulation 240-Lead Thermally Enhanced MQFP Package 225 PBGA Package 32-Bit Single-Precision and 40-Bit Extended-Precision IEEE Floating-Point Data Formats or 32-Bit FixedPoint Data Format


    Original     		PDF ADSP-2106x ADSP-21060/ADSP-21060L 240-Lead 32-Bit 40-Bit ADSP-21060KS-133 ADSP-21060KS-160 ADSP-21060KB-160 ADSP-21060 simulator program download ADSP-21060 reference manual ADSP-21060 SIMULATOR 4...20 mA ADSP21060 DESIGN AND IMPLEMENTATION 16-BIT BARREL SHIFTER ADSP21000 ADSP-21000 ADSP-21060L ADSP-21061

    SRPB

    Abstract: ADSP-21061KS-133 adsp 210xx architecture ADSP-21000 ADSP-21060 ADSP-21061 ADSP-21061L ADSP-21062 ADSP21061KS133 adsp 210xx architecture diagram
    Text: a ADSP-2106x SHARC DSP Microcomputer Family ADSP-21061/ADSP-21061L Pin-Compatible with ADSP-21060 4 Mbit and ADSP-21062 (2 Mbit) Flexible Data Formats and 40-Bit Extended Precision 32-Bit Single-Precision and 40-Bit Extended-Precision IEEE Floating-Point Data Formats


    Original     		PDF ADSP-2106x ADSP-21061/ADSP-21061L ADSP-21060 ADSP-21062 40-Bit 32-Bit 80-Bit SRPB ADSP-21061KS-133 adsp 210xx architecture ADSP-21000 ADSP-21060 ADSP-21061 ADSP-21061L ADSP-21062 ADSP21061KS133 adsp 210xx architecture diagram

    234 N02

    Abstract: 74 HTC 00 74 HTC 08 SIMULATOR 4...20 mA adsp 210xx architecture diagram TRW a-20 ADSP-21000 ADSP-21060 ADSP-21061 ADSP-21061L
    Text: a ADSP-2106x SHARC DSP Microcomputer Family ADSP-21061/ADSP-21061L Pin-Compatible with ADSP-21060 4 Mbit and ADSP-21062 (2 Mbit) Flexible Data Formats and 40-Bit Extended Precision 32-Bit Single-Precision and 40-Bit Extended-Precision IEEE Floating-Point Data Formats


    Original     		PDF ADSP-2106x ADSP-21061/ADSP-21061L ADSP-21060 ADSP-21062 40-Bit 32-Bit 80-Bit 234 N02 74 HTC 00 74 HTC 08 SIMULATOR 4...20 mA adsp 210xx architecture diagram TRW a-20 ADSP-21000 ADSP-21060 ADSP-21061 ADSP-21061L

    adsp 210xx architecture diagram

    Abstract: ADSP-21000 ADSP-21060 ADSP-21061 ADSP-21061L ADSP-21062 ADDS-2106x-EZ-Lite
    Text: a ADSP-2106x SHARC DSP Microcomputer Family ADSP-21061/ADSP-21061L Pin-Compatible with ADSP-21060 4 Mbit and ADSP-21062 (2 Mbit) Flexible Data Formats and 40-Bit Extended Precision 32-Bit Single-Precision and 40-Bit Extended-Precision IEEE Floating-Point Data Formats


    Original     		PDF ADSP-2106x ADSP-21061/ADSP-21061L ADSP-21060 ADSP-21062 40-Bit 32-Bit 80-Bit adsp 210xx architecture diagram ADSP-21000 ADSP-21060 ADSP-21061 ADSP-21061L ADSP-21062 ADDS-2106x-EZ-Lite

    IEEE mantissa exponent float DSP

    Abstract: ADSP-21160 multiplier and accumulator
    Text: C NUMERIC FORMATS Figure C-0. Table C-0. Listing C-0. Overview The DSP supports the 32-bit single-precision floating-point data format defined in the IEEE Standard 754/854. In addition, the DSP supports an extended-precision version of the same format with eight additional bits in


    Original     		PDF 32-bit 24-bit 64-Bit ADSP-21160 IEEE mantissa exponent float DSP multiplier and accumulator

    multiplier and accumulator

    Abstract: 4 bit binary multiplier ieee floating point 5 bit binary multiplier 8 BIT ALU types of binary multipliers
    Text: Numeric Formats C.1 C OVERVIEW The ADSP-2106x supports the 32-bit single-precision floating-point data format defined in the IEEE Standard 754/854. In addition, the ADSP2106x supports an extended-precision version of the same format with eight additional bits in the mantissa 40 bits total . The ADSP-2106x also


    Original     		PDF ADSP-2106x 32-bit ADSP2106x 24-bit 64-Bit multiplier and accumulator 4 bit binary multiplier ieee floating point 5 bit binary multiplier 8 BIT ALU types of binary multipliers

    Untitled

    Abstract: No abstract text available
    Text: AN ALO G D E V IC E S □ IEEE Floating-Point DSP Microprocessor FEATU RES 20 MHz IEEE Floating-Point Processor IEEE 32-Bit Single-Precision and 40-Bit Extended Single-Precision Floating-Point Formats 32-Bit Fixed-Point Formats, Integer and Fractional Separate Program and Data Buses Extended Off-Chip


    OCR Scan     		PDF 32-Bit 40-Bit 32-Word, ADSP-21020

    80387 programmers reference manual

    Abstract: weitek intel 80486 opcode sheet weitek 1167 82C301 intel 82C301 80386 programmers manual AJT20 WEITEK 3167 protected mode 80486
    Text: ABACUS 3167 FLOATING-POINT COPROCESSOR July 1990 1. Features SINGLE-CHIP FLOATING-POINT COPROCESSOR IEEE FORM AT Used with the Intel 80386 Conforms to the IEEE standard format for floating-point arithmetic in both single and double precision ANSI/IEEE Standard 754-1985


    OCR Scan     		PDF 121-pin 80387 programmers reference manual weitek intel 80486 opcode sheet weitek 1167 82C301 intel 82C301 80386 programmers manual AJT20 WEITEK 3167 protected mode 80486

    DSP-3201

    Abstract: No abstract text available
    Text: ANALOG DEVICES 32-Bit IEEE Floating-Point Chipset ADSP-3201/ADSP-3202 FEATURES Complete Chipset Implementing Floating-Point Arithmetic Fully Compatible with IEEE Standard 754 Arithmetic Operations on Three Data Formats: 32-Bit Single-Precision Floating Point


    OCR Scan     		PDF 32-Bit ADSP-3211 ADSP-3221 240ns 750mW 144-Lead OOUT31 DSP-3201

    3222S

    Abstract: No abstract text available
    Text: ANALOG DEVICES □ FEATURES Complete 40 MFLOPS Floating-Point Chipset Multiplier/Divider and ALU Fully Compatible w ith IEEE Standard 754 Arithm etic Operations on Four Data Formats: 32-Bit Single-Precision Floating-Point 64-Bit Double-Precision Floating-Point


    OCR Scan     		PDF 64-Bit ADSP-3212/ADSP-3222 32-Bit 300ns 600ns 130ns 3222S

    ADSP-3201

    Abstract: ADSP3201
    Text: ANALOG DEVICES □ 32-Bit IEEE Floating-Point Chipset ADSP-3201/ADSP-3202 FEA T U R ES Complete Chipset Implementing Floating-Point Arithmetic Fully Compatible with IEEE Standard 754 Arithmetic Operations on Three Data Formats: 32-Bit Single-Precision Floating Point


    OCR Scan     		PDF 32-Bit ADSP-3201/ADSP-3202 ADSP-3211 ADSP-3221 240ns 750mW ADSP-3201 ADSP3201

    ADSP-3201

    Abstract: ADSP-3221 ADSP-1401 adsp3201 ADSP3202 ADSP-3202 ADSP-3128 ADSP3210 HB FULLER ADSP-3210
    Text: ANALOG DEVICES 32-Bit IEEE Floating-Point Chipset ADSP-3201/ADSP-3202 FEATURES Com plete Chipset Im plementing Floating-Point Arithm etic Fully Com patible w ith IEEE Standard 754 A rithm etic Operations on Three Data Formats: 32-Bit Single-Precision Floating Point


    OCR Scan     		PDF 32-Bit ADSP-3201/ADSP-3202 ADSP-3211 ADSP-3221 240ns 750mW ADSP-3201 ADSP-1401 adsp3201 ADSP3202 ADSP-3202 ADSP-3128 ADSP3210 HB FULLER ADSP-3210

    Untitled

    Abstract: No abstract text available
    Text: ANALOG DEVICES □ 64-Bit IEEE Floating-Point Chipset ADSP-3212/ADSP-3222 FEATURES Com plete 40 MFLOPS Floating-Point Chipset M ultiplier/D ivider and ALU Fully Com patible w ith IEEE Standard 754 A rithm etic Operations on Four Data Formats: 32-Bit Single-Precision Floating-Point


    OCR Scan     		PDF 64-Bit ADSP-3212/ADSP-3222 32-Bit 300ns 600ns 130ns

    ADSP-3212

    Abstract: HI2023 ADSP32xx ADSP-3221 4106 "pin-compatible" ADSP-3210 adsp3222 ADSP-3222 CHIP SM 4108
    Text: ANALOG D EVICES □ 64-Bit IEEE Floating-Point Chipset " ADSP-3212/ADSP-3222 FEATURES Complete 40 MFLOPS Floating-Point Chipset M ultiplier/D ivider and ALU Fully Com patible w ith IEEE Standard 754 Arithm etic Operations on Four Data Formats: 32-Bit Single-Precision Floating-Point


    OCR Scan     		PDF 64-Bit ADSP-3212/ADSP-3222 32-Bit 300ns 600ns 130ns ADSP-3212 HI2023 ADSP32xx ADSP-3221 4106 "pin-compatible" ADSP-3210 adsp3222 ADSP-3222 CHIP SM 4108

    c3200 BL

    Abstract: TMC3200 nana j12 ir TMC3201 marking CYN C3200 equivalent TMC3200G5A
    Text: TRYw TMC3200, TMC3201 CM O S Floating-Point Arithmetic Unit and Multiplier 32/34 Bits The TMC3200, an arithmetic unit, adds and subtracts floating-point numbers expressed in IEEE 32-bit single­ precision format or extended-range 34-bit format. Conversions between floating-point and 24-bit two'scomplement integer fixed-point representations are


    OCR Scan     		PDF TMC3200, TMC3201 32-bit 34-bit 24-bit TMC3201, TMC32Q0, TMC3200 TMC3201 c3200 BL nana j12 ir marking CYN C3200 equivalent TMC3200G5A

    7C602

    Abstract: CY7C601
    Text: CY7C602A CYPRESS SEMICONDUCTOR Features • Direct interface to CY7C601 integer unit • Direct interface to CY7C157 Cache Storage Unit CSU • FullcompliancewithANSI/IEEE-754 standard for binary floating-point arithmetic • Supports single and double precision


    OCR Scan     		PDF CY7C602A CY7C601 CY7C157 FullcompliancewithANSI/IEEE-754 64-bit 32-bit 144-pin 7C602

    B41301

    Abstract: B2110A "Bipolar Integrated Technology" 51 ti jbr I321 B211 B2130 B3130 B4130 TI31
    Text: Bipolar Integrated Technology, Inc. B2130/B3130/B41301 Advance Information Single Chip Floating Point Processors Description Features Single chip solution for support of ANSI/IEEE STD. 754 single and double precision, and DEC F&G formats 10 ns (worst case) Pipeline mode for maximum throughput


    OCR Scan     		PDF B2130/B3130/B41301 64-bit 32-bit B2110A/B2120A B3110A/B3120A B41301 B2110A "Bipolar Integrated Technology" 51 ti jbr I321 B211 B2130 B3130 B4130 TI31

    Cy7C601

    Abstract: STD-745-1985 cy7c601a
    Text: CY7C602A CYPRESS SEMICONDUCTOR Features • Direct interface to CY7C601 integer unit • Direct interface to CY7C157 Cache Storage Unit CSU • Full compliance with ANSI/IEEE-754 standard for binary floating-point arithmetic • Supports single and double precision


    OCR Scan     		PDF CY7C602A CY7C601 CY7C157 ANSI/IEEE-754 64-bit 32-bit 144-pin CY7C602A STD-745-1985 cy7c601a

    CY7C601

    Abstract: No abstract text available
    Text: CYPRESS SEMICONDUCTOR 4LE » a s a ^ b L S - \2 .- 5 CYPRESS SEMICONDUCTOR Direct interface to CY7C601 integer unit Dircct interface to CY7C157 Caciie Storage Unit CSU Full compliance with ANSI/IEEE-754 standard for binary floating-point arithm etic Supports single and double precision


    OCR Scan     		PDF CY7C602A CY7C601 CY7C157 ANSI/IEEE-754 64-bit 32-bit