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    IEEE 802.3 CLAUSE 2 Search Results

    IEEE 802.3 CLAUSE 2 Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    LBAA0QB1SJ-295 Murata Manufacturing Co Ltd SX1262 MODULE WITH OPEN MCU Visit Murata Manufacturing Co Ltd
    GRM-KIT-OVER100-DE-D Murata Manufacturing Co Ltd 0805-1210 over100uF Cap Kit Visit Murata Manufacturing Co Ltd
    LBUA5QJ2AB-828 Murata Manufacturing Co Ltd QORVO UWB MODULE Visit Murata Manufacturing Co Ltd
    LXMSJZNCMH-225 Murata Manufacturing Co Ltd Ultra small RAIN RFID chip tag Visit Murata Manufacturing Co Ltd
    LXMS21NCMH-230 Murata Manufacturing Co Ltd Ultra small RAIN RFID chip tag Visit Murata Manufacturing Co Ltd

    IEEE 802.3 CLAUSE 2 Datasheets Context Search

    Catalog Datasheet Type Document Tags PDF

    Si3402

    Abstract: AN313U FA2805CA Si3402ISO-C4 Si3402 evb poe pse Si3402 evb datasheet Si3400 Si3401 AN296
    Text: AN313 U SING T H E Si3402 I N H IGH P OWER A PPLICATIONS 1. Introduction With the ratification of the 802.3at amendment to IEEE Std 802.3 clause 33 for Power over Ethernet PoE , the PoE standard now allows for Powered Device (PD) applications drawing up to 25.5 W of input power.


    Original     		AN313 Si3402 AN313U FA2805CA Si3402ISO-C4 Si3402 evb poe pse Si3402 evb datasheet Si3400 Si3401 AN296 PDF

    Si3402

    Abstract: Si3400 Si3401 "Power over Ethernet" AN314
    Text: AN314 P OWER C OMBINING C IRCUIT FOR POE F O R UP TO 18.5 W O UTP UT 1. Introduction IEEE STD 802.3 -2008 Clause 33 is the standard for supplying Power over the Ethernet cable. In some applications, it may be desirable to combine power from two separate cables, either for redundancy or to provide


    Original     		AN314 3TM-2008 Si3402 Si3402 Si3400 Si3401 "Power over Ethernet" AN314 PDF

    An Introduction to Auto-Negotiation

    Abstract: 1000BASE-X TINY transformer abstract
    Text: White Paper Making of IEEE 802.3 Compliant Equipment - A Discussion on Interoperability of Ethernet Over Copper Leo Chang Application Engineering Enterprise Network Business Unit PC and Networking Group December 11, 2003  2003 National Semiconductor Corporation. All rights reserved.


    Original     		10gea org/GEA1000BASET1197 com/indepth/indepth050800-1 com/sys/c/pp/OEG20030724S0032 edu/pub/gec/training/1000tcable An Introduction to Auto-Negotiation 1000BASE-X TINY transformer abstract PDF

    SFF-8665

    Abstract: TIA-604-5
    Text: WWW.PSM4.ORG 100G PSM4 Specification Parallel Single Mode 4 lane 9/15/2014 Version 2.0 September 15, 2014 100G PSM4 Specification This technical document has been created by the PSM4 MSA group. However it is not a warranted document, each transceiver supplier will have their own datasheet. If the user wishes to find a


    Original     		PDF

    1000BASE-T2

    Abstract: MDIO clause 22 clause 22 phy registers wishbone RD1074 MDIO MDIO controller 3 to 8 bit decoder vhdl IEEE format LCMXO640C-4T100C 100Base-T2
    Text: Accessing Control Registers Through the MDIO Bus February 2010 Reference Design RD1074 Introduction Management Data Input/Output Interfaces, or MDIO, are specified in the IEEE 802.3 standard. Their primary application is to provide a Serial Management Interface SMI to transfer management data between an Ethernet Media


    Original     		RD1074 LCMXO640C-4T100C 1-800-LATTICE 1000BASE-T2 MDIO clause 22 clause 22 phy registers wishbone RD1074 MDIO MDIO controller 3 to 8 bit decoder vhdl IEEE format 100Base-T2 PDF

    sgmii xilinx

    Abstract: traffic light controller vhdl coding sgmii sfp virtex IEEE 802.3 Clause 38 vhdl code for ethernet mac spartan 3 ENG-46158 1000BASE-X IEEE 802.3 Clause 39 VHDL code for traffic light controller sgmii mode sfp
    Text: Ethernet 1000BASE-X PCS/PMA or SGMII v10.2 DS264 June 24, 2009 Product Specification Introduction LogiCORE IP Facts Core Specifics The LogiCORE IP Ethernet 1000BASE-X PCS/PMA or SGMII core provides a flexible solution for connection to an Ethernet Media Access Controller MAC or


    Original     		1000BASE-X DS264 1000BASE-X ENG-46158) sgmii xilinx traffic light controller vhdl coding sgmii sfp virtex IEEE 802.3 Clause 38 vhdl code for ethernet mac spartan 3 ENG-46158 IEEE 802.3 Clause 39 VHDL code for traffic light controller sgmii mode sfp PDF

    ENG-46158

    Abstract: clause 37 AN3869 IEEE 802.3 Clause 27 eTSEC GMII Initial "IEEE 802.3" "Clause 27" RGMII to SGMII PHY sgmii specification ieee sgmii MPC8544
    Text: Freescale Semiconductor Application Note Document Number: AN3869 Rev. 0, 06/2009 Implementing SGMII Interfaces on the PowerQUICC III by 1 Networking and Multimedia Group Freescale Semiconductor, Inc. Austin, TX Introduction SGMII is a serial interface for gigabit Ethernet that replaces


    Original     		AN3869 ENG-46158 clause 37 AN3869 IEEE 802.3 Clause 27 eTSEC GMII Initial "IEEE 802.3" "Clause 27" RGMII to SGMII PHY sgmii specification ieee sgmii MPC8544 PDF

    verilog code for MII phy interface

    Abstract: MII PHY verilog code for phy interface crc verilog code 16 bit ethernet mac verilog testbench vhdl code for phy interface 2V500FG456-4
    Text: PE-MACMII Dual-speed 10/100 Mbps Ethernet MAC March 11, 2002 Product Specification AllianceCORE Facts Alcatel Technology Leasing Group 11707 East Sprague, Suite 306 Spokane, WA 99206 Phone: +1 509-777-7604, +1 509-777-7330 Fax: +1 509-777-7006 end-enterprise-ipinfo@ind.alcatel.com


    Original     		10Base-T 100Base-TX 100Base-FX 100Base-T4 16-bit verilog code for MII phy interface MII PHY verilog code for phy interface crc verilog code 16 bit ethernet mac verilog testbench vhdl code for phy interface 2V500FG456-4 PDF

    Internal diagram of ic 7495

    Abstract: LU3X54FTL IC 7495 pin configuration
    Text: Product Brief May 1998 LU3X54FTL QUAD-FET for 10Base-T/100Base-TX/FX Features 100 Mbits/s FX Transceiver 10 Mbits/s Transceiver • Compatible with IEEE 802.3U 100Base-FX standard ■ Reuses existing twisted-pair I/O pins for compatible fiber-optic transceiver pseudo-ECL PECL


    Original     		LU3X54FTL 10Base-T/100Base-TX/FX 100Base-FX LU3X54FTL 10Base-T PN98-155LAN Internal diagram of ic 7495 IC 7495 pin configuration PDF

    the RMII Consortium Specification

    Abstract: RMII Specification JUPITER* application notes RMII Consortium Broadcom Cross Reference Search ethernet mdio circuit diagram P802 RMII PHY RMII Specification revision 1.2 RMII Specification Rev1.0 consortium
    Text: March 20, 1998 Sponsored By: TM RMIITM Specification 1.0 Overview and Architecture This document comprises a low pin count Reduced Media Independent InterfaceTM RMIITM specification intended for use between Ethernet PHYs and Switch ASICs. Under IEEE 802.3u [2] an MII comprised of 16 pins for data and control is defined. In


    Original     		PDF

    connector RJ45 CAT-6

    Abstract: tellabs AN380 pin details of FET RJ45 SMALL NSG435 Si3452 E501B
    Text: AN380 ROBUST ELECTRICAL SURGE IMMUNITY FOR POE PSES T H R O U G H I N T E G R A T E D P R O TE C T I O N 1. Introduction The Si3452 PoE controller integrates a protection clamp on the detection output pin. In normal use, the detection output pin is tied to the FET output pin. The protection clamp is a diode clamp to earth ground for positive going


    Original     		AN380 Si3452 connector RJ45 CAT-6 tellabs AN380 pin details of FET RJ45 SMALL NSG435 E501B PDF

    Internal diagram of ic 7495

    Abstract: LU3X54FT "Fast Link Pulse"
    Text: Product Brief May 1998 LU3X54FT QUAD-FET for 10Base-T/100Base-TX/FX Features 100 Mbits/s FX Transceiver 10 Mbits/s Transceiver • Compatible with IEEE 802.3U 100Base-FX standard ■ Reuses existing twisted-pair I/O pins for compatible fiber-optic transceiver pseudo-ECL PECL


    Original     		LU3X54FT 10Base-T/100Base-TX/FX 100Base-FX LU3X54FT 10Base-T PN98-140LAN Internal diagram of ic 7495 "Fast Link Pulse" PDF

    PLRXPL-SC-S43-22-N

    Abstract: PLRXPL-SC-S43 SFf-8431 PLRXPL-SC-S43-xx-N sc om2 GR-468 IEC60825-1 RD12 "network interface cards"
    Text: COMMUNICATIONS MODULES & SUBSYSTEMS 10 G SFP+ 850 nm Limiting Transceiver, 10 Gigabit Ethernet Compliant PLRXPL-Sx-S43-22-N Series Key Features • Compliant to industrywide, 10 G link specifications • Uses a highly reliable, 850 nm oxide VCSEL • Lead-free and RoHS 6/6-compliant, with allowed exemptions


    Original     		PLRXPL-Sx-S43-22-N 1-800-498-JDSU 800-5378-JDSU PLRXPL-SC-S43-22-N PLRXPL-SE-S43-22-N 498-JDSU 5378-JDSU PLRXPL-SC-S43-22-N PLRXPL-SC-S43 SFf-8431 PLRXPL-SC-S43-xx-N sc om2 GR-468 IEC60825-1 RD12 "network interface cards" PDF

    the RMII Consortium Specification

    Abstract: LC10 LC100 LS10 LS100 LU3X36FTR PN99-054LAN RMII Consortium
    Text: Product Brief March 1999 LU3X36FTR HEX-FET Fast Ethernet Transceiver for 10Base-T/100Base-TX/FX Overview The LU3X36FTR is a six-channel, single-chip complete transceiver designed specifically for dual-speed 10Base-T, 100Base-TX, and 100Base-FX switches and repeaters. It supports simultaneous operation in


    Original     		LU3X36FTR 10Base-T/100Base-TX/FX LU3X36FTR 10Base-T, 100Base-TX, 100Base-FX 100Base-FX. the RMII Consortium Specification LC10 LC100 LS10 LS100 PN99-054LAN RMII Consortium PDF

    MFR62340A-J

    Abstract: MFR62340A-JO MFT62340A-J PS12 Do12c conductive strip tfc 719 zo100
    Text: MFR62340A-J Parallel Fiber Receiver Datasheet DS5397 ISSUE 3.0 December 2001 Ordering Information MFR62340A-JO MPO/MTP Connector Applications • • • • • Features • • • • • Data rate 155Mbps to 2.5Gbps per channel 12 parallel channels, total 30Gbps capacity


    Original     		MFR62340A-J DS5397 MFR62340A-JO 155Mbps 30Gbps 400MHz MFT62340A-J MFT62340A-J MFR62340A-J MFR62340A-JO PS12 Do12c conductive strip tfc 719 zo100 PDF

    bcm54640

    Abstract: bcm8727 bcm57712 10G-KR BCM8481 M 57712 57712 Auto-Negotiation 10Gbase kr BCM5464 netxtreme
    Text: BCM57712 Brief 10 Gbps Dual-Port TOE, iSCSI, FCoE, and RDMA PCI-SIG SR-IOV x8 PCI Express® Gen-2 Controller SUMMARY OF BENEFITS FEATURES • Media Interfaces • Integrated dual 10 Gbps MAC and dual XAUI /10GBASE-CX4/ 10GBASE-KX4 • Integrated quad 1000BASE-X/SGMII operation in 4x1G mode


    Original     		BCM57712 XAUITM/10GBASE-CX4/ 10GBASE-KX4 1000BASE-X/SGMII Mbit/10 BCM57712. 57712-PB00-R bcm54640 bcm8727 bcm57712 10G-KR BCM8481 M 57712 57712 Auto-Negotiation 10Gbase kr BCM5464 netxtreme PDF

    MAX24287

    Abstract: RGMII-1000 switch SGMII MII GMII 1000base SX transmitter sc ENG-46158 TF401
    Text: Data Sheet January 2013 MAX24287 1Gbps Parallel-to-Serial MII Converter General Description The MAX24287 is a flexible, low-cost Ethernet interface conversion IC. The parallel interface can be configured for GMII, RGMII, TBI, RTBI, or 10/100 MII, while the serial interface can be configured for


    Original     		MAX24287 25Gbps 1000BASE-X 1000BASE-T RGMII-1000 switch SGMII MII GMII 1000base SX transmitter sc ENG-46158 TF401 PDF

    10GBASE-T

    Abstract: RJ45 LAN port of motherboard CAT7 cables sgmii switch LDPC encoder APM96895 MACsec APM9689x 10gb RJ45 SMALL
    Text: Triveni Dual/Quad Port 10GBASE-T PHY PREL I M IN ARY PRO DU CT BRI EF The Triveni APM9689x family includes integrated dual and quad port PHYs supporting IEEE 802.3 10GBASE-T operation. Based on 40nm process technology and a state-of-the-art programmable DSP engine, the device is designed to


    Original     		10GBASE-T APM9689x RJ45 LAN port of motherboard CAT7 cables sgmii switch LDPC encoder APM96895 MACsec 10gb RJ45 SMALL PDF

    Untitled

    Abstract: No abstract text available
    Text: September 26, 1997 Reduced MII interface Sponsored By: N 1.0 Overview and Architecture This document specifies a low pin count Reduced Media Independent Interface (RMII) intended for use between Ethernet PHYs and Switch or Repeater ASICs. Under IEEE 802.3u [2] an MII comprised of 16 pins for data and control is defined. In devices


    Original     		100BASE-T. PDF

    MDIO clause 45

    Abstract: MDIO clause 22 verilog code for mdio protocol vhdl code SECDED avalon mdio register RTL code for ethernet TB D83 diode IEEE803 10 gbps transceiver testbench of an ethernet transmitter in verilog
    Text: 10-Gbps Ethernet Reference Design User Guide 101 Innovation Drive San Jose, CA 95134 www.altera.com IP Core Version: Document Date: 10.0 July 2010 i–2 July 2010 UG-01076-2.0 Altera Corporation 10-Gbps Ethernet Reference Design User Guide 1. 10-Gbps Ethernet IP Datasheet


    Original     		10-Gbps UG-01076-2 MDIO clause 45 MDIO clause 22 verilog code for mdio protocol vhdl code SECDED avalon mdio register RTL code for ethernet TB D83 diode IEEE803 10 gbps transceiver testbench of an ethernet transmitter in verilog PDF

    Untitled

    Abstract: No abstract text available
    Text: Full Duplex 84C24 Quad 10Base-T Ethernet Media Interface Adapter Technology Incorporated PRELIMINARY June 18, 1996 SEEQ Full Duplex Designation Note: Check for latest Data Sheet revision before starting any designs. Full Duplex Call SEEQ Technology 510 226-7400 x3051.


    OCR Scan     		84C24 10Base-T x3051. MD400147/A N004/A PDF

    130nm CMOS

    Abstract: P802 TLK3118 MDIO clause 45 MDIO clause 45 specification
    Text: TLK3118 REDUNDANT XAUI TRANSCEIVER SLLS609 − JANUARY 2004 D D D D D D D D D TLK3118 TDP/N[3:0]0 TCLK RDP/N[3:0]0 4 4 TD 31.0 TC(3.0) RCLK RD(31.0) TDP/N[3:0]1 RC(3.0) RDP/N[3:0]1 4 4 description The TLK3118 is a flexible, redundant XAUI serial transceiver that is compliant to 10-Gbps Ethernet XAUI


    Original     		TLK3118 SLLS609 TLK3118 10-Gbps 130nm CMOS P802 MDIO clause 45 MDIO clause 45 specification PDF

    the RMII Consortium Specification

    Abstract: MDIO clause 45 specification MDIO clause 22 RMII Consortium SMII specification LC10 LC100 LS10 LS100 LU3X312FTR
    Text: Product Brief June 1999 LU3X312FTR 12-Port Transceiver for 10Base-T/100Base-TX/FX Overview The LU3X312FTR is an twelve-channel, single-chip complete transceiver designed specifically for dualspeed 10Base-T, 100Base-TX, and 100Base-FX switches and repeaters. It supports simultaneous


    Original     		LU3X312FTR 12-Port 10Base-T/100Base-TX/FX LU3X312FTR 10Base-T, 100Base-TX, 100Base-FX 100Base-FX. the RMII Consortium Specification MDIO clause 45 specification MDIO clause 22 RMII Consortium SMII specification LC10 LC100 LS10 LS100 PDF

    PLRXPL-VC-S43-23-N

    Abstract: SFf-8431 GR-468 IEC60825-1 RD12 RIN12OMA 10G TOSA
    Text: COMMUNICATIONS MODULES & SUBSYSTEMS 10 G SFP+ 850 nm Limiting Transceiver, 10 Gigabit Ethernet Compatible PLRXPL-Vx-S43-23-N Series Key Features • Compatible with 10 G links • Uses a highly reliable, 850 nm oxide VCSEL • Lead-free and RoHS 6/6-compliant, with allowed exemptions


    Original     		PLRXPL-Vx-S43-23-N 1-800-498-JDSU 800-5378-JDSU PLRXPL-VC-S43-23-N 498-JDSU 5378-JDSU PLRXPL-VC-S43-23-N SFf-8431 GR-468 IEC60825-1 RD12 RIN12OMA 10G TOSA PDF