Untitled
Abstract: No abstract text available
Text: I Integrated Dev ice le ch n o lo g y. Inc 128K x 8 SRAM WITH LATCHED/ BUFFERED ADDRESS LINES, LATCHED/BUFFERED DATAm LINES AND REGISTERED DATA0U TLlNES IDT7M823 D A T A i n is controlled by its own enable, LEDIN. With this line in the high state, the latch is in the transparent or buffer mode. All
|
OCR Scan
|
PDF
|
IDT7M823
20MHz
IDT7M823
-200mV
128KX
|
Untitled
Abstract: No abstract text available
Text: 1 MEGABIT 128K x 8 REGISTERED/BUFFERED/ LATCHED CMOS STATIC RAM SUBSYSTEMS IDT7M824 FAMILY FEATURES: DESCRIPTION: • High-density 1024K-bit (128K x 8-bit) CMOS static RAM modules with registered/buffered/latched addresses and l/Os The IDT7M824 fam ily is a set of 1024K-bit (128K x 8-bit) high
|
OCR Scan
|
PDF
|
1024K-bit
-15mA
64-pin,
IDT49C802
IDT49C802
|
Untitled
Abstract: No abstract text available
Text: INTEGRATED DEVICE ^7 4825771 INTEGRATED D E § 4025771 Q00E7T4 5 DEVICE 97D 128K X 8 SRAM WITH LATCHED/ BUFFERED ADDRESS LINES, LATCHED/BUFFERED DATAm LINES AND REGISTERED DATAo u tLINES FEATURES: • L atch ed a n d b u ffe re d a dd re ss lines • L atch ed a n d b u ffe re d in p u t d ata lines
|
OCR Scan
|
PDF
|
Q00E7T4
IDT7M823
-20QmV
MS2S771
IDT7M823
|
IDT7M824
Abstract: No abstract text available
Text: INT EGR AT E» DEVICE T7 4 8 25 77 1 I N T E G R A T E D DEVI CE " Î ËJ 4055771 Q0027Ö1 4 J “ 97D 0 2 7 8 Ï 1 M EGABIT 128K x 8) R EG ISTE R ED /B U FFER ED / LATCHED C M O S STATIC RAM SUB SYSTEM S D/ T-46-23-14 IDT7M824 FAMILY FEATURES: DESCRIPTION:
|
OCR Scan
|
PDF
|
Q0027
T-46-23-14
1024K-blt
64-pfn,
IDT49C802
IDT7M824
|