C3264
Abstract: RAM-6A
Text: 128K x 8 SRAM WITH LATCHED/ BUFFERED ADDRESS LINES, REGISTERED DATA|N LINES AND LATCHED/BUFFERED DATA0UT LINES IDT7M822 CS and WE data that meets the specified set-up time will be latched when LE goes low. DATA in is controlled by its own clock, CPDIN. When ENDIN
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IDT7M822
20MHz
IDT7M822
-200mV
C3264
RAM-6A
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Untitled
Abstract: No abstract text available
Text: 1 MEGABIT 128K x 8 REGISTERED/BUFFERED/ LATCHED CMOS STATIC RAM SUBSYSTEMS IDT7M824 FAMILY FEATURES: DESCRIPTION: • High-density 1024K-bit (128K x 8-bit) CMOS static RAM modules with registered/buffered/latched addresses and l/Os The IDT7M824 fam ily is a set of 1024K-bit (128K x 8-bit) high
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1024K-bit
-15mA
64-pin,
IDT49C802
IDT49C802
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IDT7198
Abstract: No abstract text available
Text: INTEGRATE» DEVICE T7 4825771 I NTEGRATED D Ë J ^1055771 00027^1 97D DE V I C E 02791 D T-46-23-14 Integrateci DeviceTêchnok^y. Inc. 128K x 8 SRAM WITH LATCHED/ BUFFERED ADDRESS LINES, REGISTERED DATAm LINES AND LATCHED/BUFFERED DATA0Ut LINES CS and WE data that meets the specified set-up time will be
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T-46-23-14
20MHz
IDT7M822
-200m
5S771
IDT7198
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IDT7M824
Abstract: No abstract text available
Text: INT EGR AT E» DEVICE T7 4 8 25 77 1 I N T E G R A T E D DEVI CE " Î ËJ 4055771 Q0027Ö1 4 J “ 97D 0 2 7 8 Ï 1 M EGABIT 128K x 8) R EG ISTE R ED /B U FFER ED / LATCHED C M O S STATIC RAM SUB SYSTEM S D/ T-46-23-14 IDT7M824 FAMILY FEATURES: DESCRIPTION:
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Q0027
T-46-23-14
1024K-blt
64-pfn,
IDT49C802
IDT7M824
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