54175
Abstract: 74L02
Text: LO W -P O W ER S E R I E S 5 4 LS /74 LS S C H O T T K Y - C L A M P E D T R A N S I S T O R - T R A N S I S T O R LO G IC SCHOTTKY+ TTL MS! _ B U L L E T IN N O . D L -S 7 2 1 1 7 7 7, S E P T E M B E R 1972 FOR LOW-POWER, H IG H -PER FO R M A N C E D IG IT A L SYSTEMS
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54LS/74LS
54175
74L02
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IC 74LS14
Abstract: IC TTL 74 ls 04 ic 74ls13 74LS14
Text: fò MOTOROLA SN54/74LS13 SN54/74LS14 D E S C R I P T I O N — The S N 5 4 L S /7 4 L S 1 3 and S N 5 4 L S /7 4 L S 1 4 c o n ta in logic g ate s/in v erters w h ic h accept standard TTL input sig n a ls and provide standard TTL output levels. They are capable o f transform ing
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SN54/74LS13
SN54/74LS14
IC 74LS14
IC TTL 74 ls 04
ic 74ls13
74LS14
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74ls379
Abstract: No abstract text available
Text: < 3 > MOTOROLA OCTAL D FLIP-FLOP WITH ENABLE; HEX D FLIP-FLOP WITH ENABLE; 4-BIT D FLIP-FLOP WITH ENABLE The SN54/74LS377 is an 8-bit register built using advanced Low Power Schottky technology. This register consists of eight D-type flip-flops with a buffered common clock and a buffered common clock enable.
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SN54/74LS377
SN54/74LS378
SN54/74LS174,
SN54/74LS379
SN54/74LS175
Flop4LS378
SN54/74LS379
SN54/74LS377
SN54/74LS378
74ls379
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74LS164
Abstract: all gate ic data 74
Text: 8 < > MOTOROLA SN54/74LS164 SERIAL-IN PARALLEL-OUT SHIFT REGISTER The S N 54/74LS 164 is a high speed 8-Bit Serial-ln Parallel-Out Shift Regis ter. Serial data is entered through a 2-Input AND gate synchronous with the LOW to HIGH transition of the clock. The device features an asynchronous
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SN54/74LS164
54/74LS
SN54/74LS164
74LS164
all gate ic data 74
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pin diagram of IC 74LS373
Abstract: IC TTL 74 ls 04 IC 74ls373 ls374 74LS374 74LS373 74ls373 pin diagram of IC 74LS374
Text: Q M O T O R O L A SN54/74LS373 SN54/74LS374 D E S C R I P T I O N — The S N 5 4 L S /7 4 L S 3 7 3 consists of eioht latches w ith 3-state outputs for bus organized system applications. The flipflops appear transparent to the data (data changes asynchronous^ )
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SN54/74LS374
pin diagram of IC 74LS373
IC TTL 74 ls 04
IC 74ls373
ls374
74LS374 74LS373 74ls373
pin diagram of IC 74LS374
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w081
Abstract: No abstract text available
Text: M MOTOROLA SN 5 4 / 7 4 L S 1 7 0 D E S C R IP T IO N — The TTL/M SI SN 54 LS/7 4 LS17 0 is a high-speed, low-power 4 x 4 Register File organized as four words by four bits. Separate read and write inputs, both address and enable, allow simultaneous read and write operation.
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TTL 74 pinout
Abstract: F827 MC74FXXXDW
Text: M M O T O R O L A MC54/74F827 MC54/74F828 10-BIT BUFFERS/LINE DRIVERS (WITH 3-STATE OUTPUTS) The MC54/74F827 and MC54/74F828 10-bit bus buffers provide high per formance bus interface buffering for wide data/address paths or buses carry ing parity. The 10-bit buffers have NOR output enables for maximum control
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10-BIT
MC54/74F827
MC54/74F828
TTL 74 pinout
F827
MC74FXXXDW
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MC74F574
Abstract: F374 MC74FXXXDW
Text: M M O TO R O LA . MC74F574 OCTAL D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS The MC74F574 is a high-speed, low-power octal D-type flip-flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus oriented applications. A buffered clock (CP) and Output Enable (OE) are com mon to
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MC74F574
54/74F
F374
MC74FXXXDW
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Untitled
Abstract: No abstract text available
Text: MOTOROLA SN54LS/74LS640 thru SN54LS/74LS645 D E S C R IP T IO N — The se octal bus tra n s c e iv e rs a re des ig n e d fo r a s y n c h ro n o u s tw o - w a y c o m m u n ic a tio n b e tw e e n data buses. C ontrol fu n c tio n im p le m e n ta tio n m in im iz e s e x te rn a l tim in g re q u ire m e n ts .
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SN54LS/74LS640
SN54LS/74LS645
rS641
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Untitled
Abstract: No abstract text available
Text: MOTOROLA MC54F374 MC74F374 OCTAL D-TYPE FLIP-FLOP With 3-S tate Outputs D E S C R IP T IO N — The M C 5 4 F /7 4 F 3 7 4 isa high-speed, low -pow er octal D -type flip -flo p fe a tu rin g separate D-type inputs for each flip flop and 3 -sta te o utp uts for bus oriented applications. A buffered
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MC54F374
MC74F374
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74LS145
Abstract: TS02H
Text: fQ MOTOROLA SN54/74LS145 1-OF-IO DECODER/DRIVER OPEN-COLLECTOR The S N 54/74LS145, 1-of-10 Decoder/Driver, is designed to accept BCD inputs and provide appropriate outputs to drive 10-digit incandescent displays. All outputs remain off for all invalid binary input conditions. It is
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SN54/74LS145
54/74LS145,
1-of-10
10-digit
74LS145
TS02H
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SN5474
Abstract: SN54LS74A SN54S74 SN74 SN7474 SN74LS74A SN74S74 LS74A
Text: S N 5 474, S N 5 4 LS 74 A . S N 5 4S 74, S N 7474. S N 74 LS 74 A , S N 74S 74 D U A L D -T Y P E P O S IT IV E E D G E T R IG G E R ED F LIP -FL O P S W ITH P R E S E T A N D C LE A R DECEMBER 1983 - Package Options Include Plastic "'Small Outline" Packages, Ceramic Chip Carriers
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SN5474,
SN54LS74A,
SN54S74,
SN7474.
SN74LS74A,
SN74S74
SN5474
SN54LS74A
SN54S74
SN74
SN7474
SN74LS74A
LS74A
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Untitled
Abstract: No abstract text available
Text: g M O T O R O M C54F/74F259 L A A d v a n ce Information 8-BIT ADDRESSABLE LATCH 8-BfT ADDRESSABLE LATCH FAST DESCRIPTION— The MC54F/74F259 is a high-speed 8-bit address able latch designed for general purpose storage applications in digital system s. It is a multifunctional device capable o f storing
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MC54F/74F259
93L34
MC54F/74F259
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IC 74LS190
Abstract: pin diagram of ic 74ls191 74L19 74LS190 up down decade counter pin diagram of 74LS191 74LS190 74LS191 74LS190 PIN diagram
Text: <8 > M OTOROLA SN54/74LS190 SN54/74LS191 D ESCRIPTIO N — The SN 54LS/74LS190 is a synchronous UP/DOWN BCD Decade 8421} Counter and the SN54LS/74LS191 is a syn chronous UP/DOWN Modulo-16 Binary Counter. State changes of the counters are synchronous with the LOW-to-HIGH transition of the
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54LS/74LS190
SN54LS/74LS191
Modulo-16
SN54/74LS190
SN54/74LS191
IC 74LS190
pin diagram of ic 74ls191
74L19
74LS190 up down decade counter
pin diagram of 74LS191
74LS190
74LS191
74LS190 PIN diagram
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Untitled
Abstract: No abstract text available
Text: M M O T O R O L A MC54F/74F174 HEX D FLIP-FLOP WITH MASTER RESET DESCRIPTION — T h e M C54F/74F174 is a h ig h-speed hex D flipflo p . T h e d e v ic e is used p rim a rily a s a 6-bit edg e-trig gered storage register. T h e in fo rm a tio n o n the D in p u ts is tran sferred to storage
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MC54F/74F174
C54F/74F174
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74LS75
Abstract: No abstract text available
Text: M M O T O R O L A SN54/74LS75 SN54/74LS77 D E S C R IP T IO N — T h e T T L /M S I S N 5 4 L S / 7 4 L S 7 5 an c*S N 5 4 LS /7 4 LS 7 7 are latch es used as tem porary storage for binary information between processing u n itsa n d input/output or indicator units. Inform ation present
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16-pin
74LS75
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Untitled
Abstract: No abstract text available
Text: M M O T O R O L A SN54/74LS670 D E S C R I P T I O N — The T T L /M S I S N 5 4 L S /7 4 L S 6 7 0 is a high-speed, low -pow er 4 x 4 Register File organized as four w ords by four bits. Separate read and w rite inputs, both address and enable, a llow
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SN54/74LS670
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74LS164D
Abstract: 74ls164
Text: g MOTOROLA SN54/74LS164 D E S C R I P T I O N — The S N 5 4 L S /7 4 L S 1 6 4 is a high speed 8-B it SerialIn P a ra lle l-O u t S h ift Register. S e ria l data is entered through a 2-Input A N D gate synchron ous w ith the L O W to HIGH transition of the clock.
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SN54/74LS164
74LS164D
74ls164
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Untitled
Abstract: No abstract text available
Text: M MOTOROLA. MC54/74F533 OCTAL TRANSPARENT LATCH WITH 3-STATE OUTPUTS The M C 54/74F533 consists of eight latches with 3-state outputs for bus or ganized system applications.The flip-flops appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the
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MC54/74F533
54/74F533
54/74F
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Motorola 74LS
Abstract: 74LS122
Text: M MOTOROLA SN 5 4 L S /7 4 L S 122 SN 5 4 L S /7 4 L S 123 D E S C R IP T IO N — These d-c triggered m ultivibrators feature pulse w id th control by three methods. The basic pulse w id th is programmed by selection of external resistance and capacitance values. The LS122
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LS122
/74LS
SN54LS
74LS123
Motorola 74LS
74LS122
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Tic 4148
Abstract: No abstract text available
Text: M MOTOROLA MC54F533 MC74F533 OCTAL TRANSPARENT LATCH (With 3~State Outputs) D E S C R IP T IO N — The M C 5 4 F /7 4 F 5 3 3 consists of e ight latches w ith 3-sta te outputs fo r bus organized system applications. The flip flops appear transparent to the data w hen Latch Enable (LE) is HIGH.
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MC54F533
MC74F533
Tic 4148
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Untitled
Abstract: No abstract text available
Text: g MOTOROLA SN54LS170 SN74LS170 D E S C R IP T IO N — T he T T L /M S I S N 5 4 L S / 7 4 L S 1 7 0 is a hig h -s p e e d , lo w 'p o w e r 4 x 4 R e gister File org a n iz e d as fo u r w o rd s by fo u r bits. S e p a ra te read and w r ite in p u ts , b o th ad d re ss a n d ena ble, a llo w
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Untitled
Abstract: No abstract text available
Text: M M O T O R O L A MC54F/74F537 Product Preview -l-OF-10 DECODER WITH 3-STATE OUTPUTS I-OF-IO DECODER (With 3-State Outputs) FAST DESCRIPTION — The MC54/74F537 is one-of-ten decoder/demul tiplexer with four active HIGH BCD inputs and ten mutually exclu
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MC54F/74F537
MC54/74F537
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Untitled
Abstract: No abstract text available
Text: M M O TO R O LA MC54F/74F373 OCTAL TRANSPARENT LATCH (With 3-State Outputs) OCTAL TRANSPARENT LATCH (With 3-State Outputs) D E S C R IPT IO N — The M C 5 4 R 7 4 F 3 7 3 c o n sists o f e ig h t latch es w ith 3-state o u tp u ts fo r b u s o rg an ize d system a p p lica tio ns. T h e flipflo p s a p p e a r tran sp are n t to the data w h e n Latch E n a b le (LE) is
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MC54F/74F373
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