MPC885
Abstract: mii to hdlc MPC870 MPC875 MPC880 WLAN Module MII MPC880/MPC875/MPC870
Text: Freescale Semiconductor, Inc. Fact Sheet MPC885 Family PowerQUICC Integrated Communications Processor Freescale Semiconductor, Inc. MPC885 COMMUNICATIONS PROCESSOR 8 KB I-Cache System Interface Unit Memory Controller I-MMU Embedded 8xx Core OVERVIEW
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MPC885
MPC885FAMFS/D
mii to hdlc
MPC870
MPC875
MPC880
WLAN Module MII
MPC880/MPC875/MPC870
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WLAN Module MII
Abstract: MPC870 MPC875 MPC880 MPC885
Text: Fact Sheet MPC885 Family PowerQUICC Integrated Communications Processor MPC885 COMMUNICATIONS PROCESSOR 8 KB I-Cache System Interface Unit Memory Controller I-MMU Embedded 8xx Core OVERVIEW Motorola’s PowerQUICC™ architecture containing a PowerPC™ core provides an exceptional combination of
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MPC885
MPC885FAMFS/D
WLAN Module MII
MPC870
MPC875
MPC880
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RWS 434 RF receiver
Abstract: free SMD Codebook RBS 2109 manual book IOM-2 Interface Reference Guide SMD Codebook 8259A simulator Delta Electronics dps -300HB A RDD 17-33 T1605 sad1 smd
Text: ICs for Communications DSP Oriented PBX Controller DOC PEB 20560 Version 2.1 Preliminary Data Sheet 11.97 / e .d s n / e m tor e i s duc . w n w o c w i / / : em p t ht S PEB 20560 Revision History: Current Version: Preliminary Data Sheet 11.97 Previous Version:
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PB68C
Abstract: LFSCM3GA40EP1
Text: LatticeSC Family Data Sheet DS1004 Version 01.4a, January 2007 LatticeSC Family Data Sheet Introduction November 2006 Preliminary Data Sheet DS1004 Features • High Performance FPGA Fabric • 15K to 115K four input Look-up Tables LUT4s • 132 to 942 I/Os
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DS1004
DS1004
700MHz
600Mbps
125Gbps)
105mW
LVPECL33
SC115
PB68C
LFSCM3GA40EP1
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Untitled
Abstract: No abstract text available
Text: LatticeSC Family Data Sheet DS1004 Version 01.3, August 2006 LatticeSC Family Data Sheet Introduction August 2006 Preliminary Data Sheet DS1004 Features • High Performance FPGA Fabric • 15K to 115K four input Look-up Tables LUT4s • 132 to 942 I/Os
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DS1004
DS1004
700MHz
600Mbps
125Gbps)
110mW
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Untitled
Abstract: No abstract text available
Text: LatticeSC Family Data Sheet DS1004 Version 01.4b, February 2007 LatticeSC Family Data Sheet Introduction November 2006 Preliminary Data Sheet DS1004 Features • High Performance FPGA Fabric • 15K to 115K four input Look-up Tables LUT4s • 132 to 942 I/Os
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DS1004
DS1004
700MHz
600Mbps
125Gbps)
105mW
SC115
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AD143
Abstract: NM2200 rz2 h24 SD335 RZ2 G6 AD133 RZ2 G24 BT 2323 M ic pin configuration AD313 AD303
Text: A B C D E SHEET INDEX PENTIUM II MOBILE MODULE VREG Sheet 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 TAG 4 L2 CACHE CPU 443BX NORTH BRIDGE Sheet Name Description ARCHITECTURE BLOCK DIAGRAM MMC-2 CONNECTOR CPU, DRAM I/F MMC-2 CONNECTOR (PCI/AGP I/F)
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NM2200/NMG5)
2N7002
NC7SZ08
576MHZ
FA-368
RNX13,
RNX14,
BC276
BC274
AD143
NM2200
rz2 h24
SD335
RZ2 G6
AD133
RZ2 G24
BT 2323 M ic pin configuration
AD313
AD303
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Untitled
Abstract: No abstract text available
Text: LatticeSC/M Family Data Sheet DS1004 Version 02.0, March 2008 LatticeSC/M Family Data Sheet Introduction January 2008 Preliminary Data Sheet DS1004 Features • High Performance FPGA Fabric • 15K to 115K four input Look-up Tables LUT4s • 139 to 942 I/Os
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DS1004
DS1004
700MHz
600Mbps
125Gbps)
105mW
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2-bit comparator
Abstract: LFSC3GA15E-5F900I PR77A PR55D pr94a diode transistor pt36c pt36C PB110C pb127d PB138
Text: LatticeSC/M Family Data Sheet DS1004 Version 01.8, November 2007 LatticeSC/M Family Data Sheet Introduction March 2007 Preliminary Data Sheet DS1004 Features • High Performance FPGA Fabric • 15K to 115K four input Look-up Tables LUT4s • 132 to 942 I/Os
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DS1004
DS1004
700MHz
600Mbps
125Gbps)
105mW
2-bit comparator
LFSC3GA15E-5F900I
PR77A
PR55D
pr94a diode
transistor pt36c
pt36C
PB110C
pb127d
PB138
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Untitled
Abstract: No abstract text available
Text: LatticeSC/M Family Data Sheet DS1004 Version 01.9, January 2008 LatticeSC/M Family Data Sheet Introduction January 2008 Preliminary Data Sheet DS1004 Features • High Performance FPGA Fabric • 15K to 115K four input Look-up Tables LUT4s • 132 to 942 I/Os
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DS1004
DS1004
700MHz
600Mbps
125Gbps)
105mW
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Untitled
Abstract: No abstract text available
Text: LatticeSC/M Family Data Sheet DS1004 Version 01.6, August 2007 LatticeSC/M Family Data Sheet Introduction March 2007 Preliminary Data Sheet DS1004 Features • High Performance FPGA Fabric • 15K to 115K four input Look-up Tables LUT4s • 132 to 942 I/Os
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DS1004
DS1004
700MHz
600Mbps
125Gbps)
105mW
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Untitled
Abstract: No abstract text available
Text: LatticeSC Family Data Sheet Version 01.0, February 2006 LatticeSC Family Data Sheet Introduction February 2006 Preliminary Data Sheet Features • High Performance FPGA Fabric • 15K to 115K four input Look-up Tables LUT4s • 132 to 942 I/Os • 700MHz global clock; 1GHz edge clocks
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700MHz
622Mbps
125Gbps)
100mW
TN1101)
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Untitled
Abstract: No abstract text available
Text: LatticeSC Family Data Sheet Version 01.1, April 2006 LatticeSC Family Data Sheet Introduction April 2006 Preliminary Data Sheet Features • High Performance FPGA Fabric • 15K to 115K four input Look-up Tables LUT4s • 132 to 942 I/Os • 700MHz global clock; 1GHz edge clocks
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700MHz
622Mbps
125Gbps)
100mW
TN1101)
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transistor pt36c
Abstract: stm cl-30 datasheet transistor pt36C transistor pt42c pt36c PT42C pt8a ap13.6 diode PT35c transistor PR25D
Text: Data Sheet March, 2003 ORCA Series 4 FPGAs Introduction • Traditional I/O selections: — LVTTL 3.3V and LVCMOS (2.5 V and 1.8 V) I/Os. — Per pin-selectable I/O clamping diodes provide 3.3 V PCI compliance. — Individually programmable drive capability:
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sink/12
OR4E06-1BM680I
transistor pt36c
stm cl-30
datasheet transistor pt36C
transistor pt42c
pt36c
PT42C
pt8a
ap13.6 diode
PT35c transistor
PR25D
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PT18C
Abstract: k62M k72 u2
Text: Data Sheet November, 2002 ORCA Series 4 FPGAs Introduction • Traditional I/O selections: — LVTTL 3.3V and LVCMOS (2.5 V and 1.8 V) I/Os. — Per pin-selectable I/O clamping diodes provide 3.3 V PCI compliance. — Individually programmable drive capability:
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OR4E02
OR4E02-2BA352I
OR4E02-2BM416I
OR4E02-2BM680I
OR4E02-1BA352I
OR4E02-1BM416I
OR4E02-1BM680I
OR4E04-2BA352I
OR4E04-2BM416I
OR4E04-2BM680I
PT18C
k62M
k72 u2
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PB21D
Abstract: No abstract text available
Text: Data Sheet August, 2003 ORCA Series 4 FPGAs Introduction • Traditional I/O selections: — LVTTL 3.3V and LVCMOS (2.5 V and 1.8 V) I/Os. — Per pin-selectable I/O clamping diodes provide 3.3 V PCI compliance. — Individually programmable drive capability:
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OR4E04
OR4E06
PB21D
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transistor pt36c
Abstract: datasheet transistor pt36C PT35c transistor pt36c microprocessor block diagram of plc pt35c transistor pt42c PT42C transistor BC 157 PLC Communication cables pin diagram
Text: Data Sheet November, 2003 ORCA Series 4 FPGAs Introduction • Traditional I/O selections: — LVTTL 3.3V and LVCMOS (2.5 V and 1.8 V) I/Os. — Per pin-selectable I/O clamping diodes provide 3.3 V PCI compliance. — Individually programmable drive capability:
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sink/12
transistor pt36c
datasheet transistor pt36C
PT35c transistor
pt36c
microprocessor block diagram of plc
pt35c
transistor pt42c
PT42C
transistor BC 157
PLC Communication cables pin diagram
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Untitled
Abstract: No abstract text available
Text: LatticeSC Family Data Sheet DS1004 Version 01.5, March 2007 LatticeSC Family Data Sheet Introduction March 2007 Preliminary Data Sheet DS1004 Features • High Performance FPGA Fabric • 15K to 115K four input Look-up Tables LUT4s • 132 to 942 I/Os • 700MHz global clock; 1GHz edge clocks
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DS1004
DS1004
700MHz
600Mbps
125Gbps)
105mW
LFSC25
FF1020
LFSC80
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Untitled
Abstract: No abstract text available
Text: LatticeSC Family Data Sheet DS1004 Version 01.5, March 2007 LatticeSC Family Data Sheet Introduction March 2007 Preliminary Data Sheet DS1004 Features • High Performance FPGA Fabric • 15K to 115K four input Look-up Tables LUT4s • 132 to 942 I/Os • 700MHz global clock; 1GHz edge clocks
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DS1004
DS1004
700MHz
600Mbps
125Gbps)
105mW
LFSC25
FF1020
LFSC80
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Untitled
Abstract: No abstract text available
Text: LatticeSC Family Data Sheet DS1004 Version 01.5, March 2007 LatticeSC Family Data Sheet Introduction March 2007 Preliminary Data Sheet DS1004 Features • High Performance FPGA Fabric • 15K to 115K four input Look-up Tables LUT4s • 132 to 942 I/Os • 700MHz global clock; 1GHz edge clocks
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DS1004
DS1004
700MHz
600Mbps
125Gbps)
105mW
LFSC25
FF1020
LFSC80
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pt45
Abstract: No abstract text available
Text: LatticeSC Family Data Sheet DS1004 Version 01.2, June 2006 LatticeSC Family Data Sheet Introduction June 2006 Preliminary Data Sheet DS1004 Features • High Performance FPGA Fabric • 15K to 115K four input Look-up Tables LUT4s • 132 to 942 I/Os • 700MHz global clock; 1GHz edge clocks
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DS1004
DS1004
700MHz
600Mbps
125Gbps)
110mW
VCC12.
LFSC25
900-Ball
pt45
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Untitled
Abstract: No abstract text available
Text: Data Sheet January 3, 2002 ORCA Series 4 FPGAs Introduction • Traditional I/O selections: — LVTTL and LVCMOS 3.3 V, 2.5 V, and 1.8 V I/Os. — Per pin-selectable I/O clamping diodes provide 3.3 V PCI compliance. — Individually programmable drive capability:
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sink/12
DS01-174NCIP
DS01-024NCIP)
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k72 u2
Abstract: sd tray
Text: Data Sheet September, 2002 ORCA Series 4 FPGAs Introduction • Traditional I/O selections: — LVTTL and LVCMOS 3.3 V, 2.5 V, and 1.8 V I/Os. — Per pin-selectable I/O clamping diodes provide 3.3 V PCI compliance. — Individually programmable drive capability:
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anE041BM680-DB
OR4E063BA352-DB
OR4E063BM680-DB
OR4E062BA352-DB
OR4E062BM680-DB
OR4E061BA352-DB
OR4E061BM680-DB
OR4E04
OR4E06
DS01-174NCIP
k72 u2
sd tray
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pt36c equivalent
Abstract: transistor pt36c pt36c pt35c transistor pt42c datasheet transistor pt36C PT42C l22c INTEL Core i7 860 128x8 ram
Text: Data Sheet January 15, 2002 ORCA Series 4 FPGAs Introduction • Traditional I/O selections: — LVTTL and LVCMOS 3.3 V, 2.5 V, and 1.8 V I/Os. — Per pin-selectable I/O clamping diodes provide 3.3 V PCI compliance. — Individually programmable drive capability:
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256-Pin
352-Pin
416-Pin
432-Pin
680-Pin
DS01-174NCIP
DS01-024NCIP)
pt36c equivalent
transistor pt36c
pt36c
pt35c
transistor pt42c
datasheet transistor pt36C
PT42C
l22c
INTEL Core i7 860
128x8 ram
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