Untitled
Abstract: No abstract text available
Text: STC5429 Synchronous Clock for SETS DATASHEET Description Features The RoHS compliant STC5429 is a single chip clock synchronization solution for applications in SDH/SETS, SONET, and Synchronous Ethernet network elements. The device is fully compliant with ITU-T G.813 option 1 and 2,
|
Original
|
STC5429
STC5429
GR1244
GR253.
GR253
|
PDF
|
Untitled
Abstract: No abstract text available
Text: STC5455 Synchronous Clock for SETS Data sheet Description Features The RoHS 6/6 compliant STC5455 is a single chip clock synchronization solution for applications in SDH/SETS, SONET, and Synchronous Ethernet network elements. The device is fully compliant with ITU-T G.813 option 1 and 2,
|
Original
|
STC5455
STC5455
GR1244
GR253.
GR253
25MHz,
TM121
|
PDF
|
history of automatic phase selector
Abstract: space qualified synthesizer
Text: STC5420 Synchronous Clock for SETS Data sheet Description Features The RoHS 6/6 compliant STC5420 is a single chip clock synchronization solution for applications in SDH/SETS, SONET, and Synchronous Ethernet network elements. The device is fully compliant with ITU-T G.813 option 1 and 2,
|
Original
|
STC5420
GR1244
GR253.
25MHz,
STC5420
history of automatic phase selector
space qualified synthesizer
|
PDF
|
history of automatic phase selector
Abstract: R2598 ami c21 GR O11 213E ACS8510 AM27C64 EZ1086 R102 block diagram of moving message display using 805
Text: EVALUATION BOARD ACS8510 V2-EVB Advanced Communications SETS - Synchronous Equipment Timing Source Revision 2.04 March 2001 DESCRIPTION FEATURES The ACS8510 V2-EVB is an evaluation kit for exercising and evaluating the functions of the ACS8510 V2 SETS Synchronous Equipment Timing Source SDH and
|
Original
|
ACS8510
95/98/NT4
history of automatic phase selector
R2598
ami c21
GR O11
213E
AM27C64
EZ1086
R102
block diagram of moving message display using 805
|
PDF
|
Untitled
Abstract: No abstract text available
Text: STA5620A STA5620C Fully integrated RF front-end receiver for GPS applications Features • Low IF architecture fIF = 4fO ■ Minimum external components ■ VGA gain internally regulated ■ On chip programmable PLL ■ Typ. 2.7 V supply voltage ■ SPI interface
|
Original
|
STA5620A
STA5620C
QFN-32
VFQFPN32
|
PDF
|
Untitled
Abstract: No abstract text available
Text: STC5420 Synchronous Clock for SETS Data sheet Description Features The RoHS 6/6 compliant STC5420 is a single chip clock synchronization solution for applications in SDH/SETS, SONET, and Synchronous Ethernet network elements. The device is fully compliant with ITU-T G.813 option 1 and 2,
|
Original
|
STC5420
GR1244
GR253.
25MHz,
STC5420
Tm112
|
PDF
|
history of automatic phase selector
Abstract: No abstract text available
Text: STC5420 Synchronous Clock for SETS Data sheet Description Features The RoHS 6/6 compliant STC5420 is a single chip clock synchronization solution for applications in SDH/SETS, SONET, and Synchronous Ethernet network elements. The device is fully compliant with ITU-T G.813 option 1 and 2,
|
Original
|
STC5420
GR1244
GR253.
25MHz,
STC5420
TM112
history of automatic phase selector
|
PDF
|
4092MHz
Abstract: 12276M gps clock
Text: STA5620 Fully integrated RF front-end receiver for GPS applications Preliminary Data Features • Low IF architecture fIF = 4fO ■ Minimum external components ■ VGA gain internally regulated ■ On chip programmable PLL ■ Typ. 2.7V supply voltage ■
|
Original
|
STA5620
QFN-32
10MHz
40MHz.
4092MHz
12276M
gps clock
|
PDF
|
Untitled
Abstract: No abstract text available
Text: STC5420 Synchronous Clock for SETS Data sheet Description Features The RoHS 6/6 compliant STC5420 is a single chip clock synchronization solution for applications in SDH/SETS, SONET, and Synchronous Ethernet network elements. The device is fully compliant with ITU-T G.813 option 1 and 2,
|
Original
|
STC5420
GR1244
GR253.
25MHz,
STC5420
|
PDF
|
china model inverter circuit diagram
Abstract: STA5620 tcxo 16.368MHz 2.7V QFN-32 STA5620TR gps clock
Text: STA5620 Fully integrated RF front-end for GPS Preliminary Data Features • Low IF architecture fIF = 4fO ■ Minimum external components ■ VGA gain internally regulated ■ On chip programmable PLL ■ Typ. 2.7V supply voltage ■ SPI interface ■ 2kV HBM ESD protected
|
Original
|
STA5620
QFN-32
VFQFPN-32L
42MHz
092MHz.
china model inverter circuit diagram
STA5620
tcxo 16.368MHz 2.7V
STA5620TR
gps clock
|
PDF
|
STA5620
Abstract: QFN-32 STA5620TR VFQFPN32
Text: STA5620 Fully integrated RF front-end receiver for GPS applications Features • Low IF architecture fIF = 4fO ■ Minimum external components ■ VGA gain internally regulated ■ On chip programmable PLL ■ Typ. 2.7 V supply voltage ■ SPI interface
|
Original
|
STA5620
QFN-32
VFQFPN32
STA5620
STA5620TR
VFQFPN32
|
PDF
|
Untitled
Abstract: No abstract text available
Text: STA5620A STA5620C Fully integrated RF front-end receiver for GPS applications Features • Low IF architecture fIF = 4fO ■ Minimum external components ■ VGA gain internally regulated ■ On chip programmable PLL ■ Typ. 2.7 V supply voltage ■ SPI interface
|
Original
|
STA5620A
STA5620C
QFN-32
VFQFPN32
|
PDF
|
STA5620C
Abstract: No abstract text available
Text: STA5620A STA5620C Fully integrated RF front-end receiver for GPS applications Features • Low IF architecture fIF = 4fO ■ Minimum external components ■ VGA gain internally regulated ■ On chip programmable PLL ■ Typ. 2.7 V supply voltage ■ SPI interface
|
Original
|
STA5620A
STA5620C
QFN-32
VFQFPN32
STA5620C
|
PDF
|
Untitled
Abstract: No abstract text available
Text: STA5620 Fully integrated RF front-end receiver for GPS applications Features • Low IF architecture fIF = 4fO ■ Minimum external components ■ VGA gain internally regulated ■ On chip programmable PLL ■ Typ. 2.7 V supply voltage ■ SPI interface
|
Original
|
STA5620
QFN-32
VFQFPN32
STA5620
VFQFPN32
|
PDF
|
|
Untitled
Abstract: No abstract text available
Text: STC5423 Synchronous Clock for SETS Data sheet Description Features The RoHS 6/6 compliant STC5423 is a single chip clock synchronization solution for applications in SDH/SETS, SONET, and Synchronous Ethernet network elements. The device is fully compliant with ITU-T G.813 option 1 and 2,
|
Original
|
STC5423
GR1244
GR253.
25MHz,
STC5423
|
PDF
|
Untitled
Abstract: No abstract text available
Text: STC5423 Synchronous Clock for SETS Data sheet Description Features The RoHS 6/6 compliant STC5423 is a single chip clock synchronization solution for applications in SDH/SETS, SONET, and Synchronous Ethernet network elements. The device is fully compliant with ITU-T G.813 option 1 and 2,
|
Original
|
STC5423
GR1244
GR253.
25MHz,
STC5423
TM114
|
PDF
|
tm114
Abstract: No abstract text available
Text: STC5423 Synchronous Clock for SETS Data sheet Description Features The RoHS 6/6 compliant STC5423 is a single chip clock synchronization solution for applications in SDH/SETS, SONET, and Synchronous Ethernet network elements. The device is fully compliant with ITU-T G.813 option 1 and 2,
|
Original
|
STC5423
GR1244
GR253.
25MHz,
STC5423
TM114
|
PDF
|
Untitled
Abstract: No abstract text available
Text: STC5423 Synchronous Clock for SETS Data sheet Description Features The RoHS 6/6 compliant STC5423 is a single chip clock synchronization solution for applications in SDH/SETS, SONET, and Synchronous Ethernet network elements. The device is fully compliant with ITU-T G.813 option 1 and 2,
|
Original
|
STC5423
GR1244
GR253.
25MHz,
STC5423
TM114
|
PDF
|
JMP19
Abstract: SK3 lamp SW-DIP-2 C5659 jmp20 EPM7128STC100-15 panel mount banana jack smd pushbutton footprint P200 ACS8947T
Text: ACS8947T JAM PLL Jitter Attenuating, Multiplying Phase-Locked Loop with Automatic Input Switch and Data Resynchronization Path ADVANCED COMMUNICATIONS COMMS & SENSING FINAL EVALUATION BOARD ACS8947T JAM PLL Evaluation Board EVB Kit About this document This document is the user guide for the ACS8947T JAM
|
Original
|
ACS8947T
ISO9001
JMP19
SK3 lamp
SW-DIP-2
C5659
jmp20
EPM7128STC100-15
panel mount banana jack
smd pushbutton footprint
P200
|
PDF
|
Untitled
Abstract: No abstract text available
Text: EV8AQ165A QUADRUPLE Analog to Digital Converter High Bandwith, Low power, Low input Swing QUAD 8-bit 1.25 GSps ADC operting up to 5 GSps Datasheet Main Features • Quad ADC with 8-bit Resolution using e2v Proprietary Analog input Cross-point Switch • •
|
Original
|
EV8AQ165A
|
PDF
|
SAA7119
Abstract: saa7154 RSN 309 W 44H SAA7154H SAA7154E SAA7118 An RTCO 7AH SPLPL9 myson mtv048 SAA7154E/V2
Text: SAA7154E; SAA7154H Multistandard video decoder with comb filter, component input and RGB output Rev. 02 — 6 December 2007 Product data sheet 1. General description The SAA7154E; SAA7154H is a high-quality multistandard video decoder supporting 10-bit Analog-to-Digital Converter ADC , enhanced PAL/NTSC comb filtering, more
|
Original
|
SAA7154E;
SAA7154H
SAA7154H
10-bit
24-bit
SAA7154E
SAA7119
saa7154
RSN 309 W 44H
SAA7118 An
RTCO 7AH
SPLPL9
myson mtv048
SAA7154E/V2
|
PDF
|
TFBGA48 thermal
Abstract: No abstract text available
Text: STA529 FFX audio codec with analog and digital inputs and 2 x 1.2 W or 2 x 100 mW HP class-D amplifier Datasheet − production data Features • Up to 96 dB dynamic range ■ Sample rates from 8 kHz to 192 kHz ™ TFBGA48 ■ FFX ■ 1.55 V to 1.95 V digital power supply
|
Original
|
STA529
TFBGA48
18-bit
90-dB
16-bit
TFBGA48 thermal
|
PDF
|
Untitled
Abstract: No abstract text available
Text: STA529 FFX audio codec with analog and digital inputs and 2 x 1.2 W or 2 x 100 mW HP class-D amplifier Datasheet − production data Features • Up to 96 dB dynamic range ■ Sample rates from 8 kHz to 192 kHz ™ TFBGA48 ■ FFX ■ 1.55 V to 1.95 V digital power supply
|
Original
|
STA529
TFBGA48
18-bit
90-dB
16-bit
|
PDF
|
STA529
Abstract: adc/microphone converter P2SC STA529Q TFBGA48 10 pin volume control
Text: STA529 FFX audio codec with analog and digital inputs and 2 x 1.2 W or 2 x 100 mW HP class-D amplifier Features Up to 96 dB dynamic range Sample rates from 8 kHz to 192 kHz FFX™ class-D driver 1.55 V to 1.95 V digital power supply 1.80 V to 3.60 V analog and I/O power supply
|
Original
|
STA529
TFBGA48
18-bit
90-dB
VFQFPN52
STA529
adc/microphone converter
P2SC
STA529Q
TFBGA48
10 pin volume control
|
PDF
|