hf1932
Abstract: HSUL-12 DDR3U DIODE CQ 618 lvds cable 20 pins rf1517 UniPHY lpddr2 SSTL-135
Text: Section II. I/O Interfaces This section provides information about Stratix V device I/O features, external memory interfaces, and high-speed differential interfaces with dynamic phase alignment DPA . This section includes the following chapters: • Chapter 5, I/O Features in Stratix V Devices
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SV51011-1
Abstract: epcq DDR3L HF1932 SV51009-1 AHDL adder subtractor
Text: Stratix V Device Handbook Volume 2: Device Interfaces and Integration Stratix V Device Handbook Volume 2: Device Interfaces and Integration 101 Innovation Drive San Jose, CA 95134 www.altera.com SV5V1-1.3 11.0 2011 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX are Reg. U.S. Pat.
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