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    HDLC MODEM Search Results

    HDLC MODEM Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    CS-DSNULW19FF-005 Amphenol Cables on Demand Amphenol CS-DSNULW19FF-005 DB9 Female to DB9 Female Null Modem Cable - Double Shielded - No Handshaking 5ft Datasheet
    CS-DSNULW29MF-005 Amphenol Cables on Demand Amphenol CS-DSNULW29MF-005 DB9 Male to DB9 Female Null Modem Cable - Double Shielded - Full Handshaking 5ft Datasheet
    CS-DSNULW19MF-010 Amphenol Cables on Demand Amphenol CS-DSNULW19MF-010 DB9 Male to DB9 Female Null Modem Cable - Double Shielded - No Handshaking 10ft Datasheet
    CS-DSNULW19MF-025 Amphenol Cables on Demand Amphenol CS-DSNULW19MF-025 DB9 Male to DB9 Female Null Modem Cable - Double Shielded - No Handshaking 25ft Datasheet
    CS-DSNULW19FF-010 Amphenol Cables on Demand Amphenol CS-DSNULW19FF-010 DB9 Female to DB9 Female Null Modem Cable - Double Shielded - No Handshaking 10ft Datasheet

    HDLC MODEM Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    hdlc

    Abstract: IEC3309 XF-HDLC RFC1619 XC4000XL HDLC controller CC318f
    Text: HDLC Controller Solutions with Spartan-II FPGAs Customer Tutorial February 2000 File Number Here Agenda Introduction HDLC Overview HDLC Controller Applications Spartan-II IP Solutions for HDLC Controllers HDLC Controller ASSPs Spartan-II Family - Programmable ASSP


    Original     		PDF

    4ppm protocol

    Abstract: CRC-16 CRC32 MC68160 MPC823 CRC-CCITT 0xFFFF 0XFFF0000 IrDA Protocol
    Text: Communication Processor Module 16.9.18.5 SCC2 APPLETALK PROGRAMMING EXAMPLE. Except for the previously discussed register programming, use the example in Section 16.9.16.14 SCC2 HDLC Programming Example #1. 16.9.19 The SCC2 in Asynchronous HDLC Mode SCC2 Asynchronous HDLC is a frame-based protocol that uses HDLC framing techniques in


    Original     		PDF MPC823 MPC823 10BASE-T) MPC823, 10BASE-T MC68160 4ppm protocol CRC-16 CRC32 CRC-CCITT 0xFFFF 0XFFF0000 IrDA Protocol

    Bi-phase-L Coding

    Abstract: CRC16 D555 MPC821 manchester differential
    Text: Communication Processor Module 16.14 SERIAL COMMUNICATION CONTROLLERS The following is a list of the SCCs’ important features: • Implements HDLC/SDLC, HDLC bus, asynchronous HDLC, BISYNC, synchronous start/stop, asynchronous start/stop UART , AppleTalk/LocalTalk, and totally


    Original     		PDF 10-Mbps MPC821 Bi-phase-L Coding CRC16 D555 manchester differential

    MPC821

    Abstract: No abstract text available
    Text: Communication Processor Module 16.14.19.2 ASYNC HDLC CHANNEL FRAME TRANSMISSION PROCESSING. The ASYNC HDLC controller is designed to work with a minimum amount of intervention from the CPU core. It operates in a similar fashion to the HDLC controller on the MPC821.


    Original     		PDF MPC821. MPC821

    Untitled

    Abstract: No abstract text available
    Text: AM186CC Raw HDLC Driver CodeKit Embedded Processor Division V1.0 - Friday, July 24, 1998 Readme File : Version 1.1 - Friday, July 24, 1998 1 Overview This CodeKit contains a raw HDLC driver for the AMD AM186CC microprocessor. This is an interrupt driven HDLC driver that allows raw unformatted HDLC traffic to be transmitted and received. A small application is


    Original     		PDF AM186CC AM79C32

    TH21C

    Abstract: TP31C hdlc 11-B DS3131 TD39
    Text: DEMO KIT AVAILABLE DS3131 BoSS 40-Port, Unchannelized Bit-Synchronous HDLC www.maxim-ic.com GENERAL DESCRIPTION FEATURES The DS3131 bit-synchronous BoSS HDLC controller can handle up to 40 channels of highspeed, unchannelized, bit-synchronous HDLC. The on-board DMA has been optimized for


    Original     		PDF DS3131 40-Port, DS3131 DS3131. TH21C TP31C hdlc 11-B TD39

    TP31C

    Abstract: 083C Cables datasheet rh16c RH25CR hdlc 11-B DS3131 TD39 TH21C rbp2
    Text: DEMO KIT AVAILABLE DS3131 BoSS 40-Port, Unchannelized Bit-Synchronous HDLC www.maxim-ic.com GENERAL DESCRIPTION FEATURES The DS3131 bit-synchronous BoSS HDLC controller can handle up to 40 channels of highspeed, unchannelized, bit-synchronous HDLC. The on-board DMA has been optimized for


    Original     		PDF DS3131 40-Port, DS3131 DS3131. TP31C 083C Cables datasheet rh16c RH25CR hdlc 11-B TD39 TH21C rbp2

    testbench verilog ram 16 x 4

    Abstract: HSCX 82525 hdlc R8051XC XC3S1500E-4 hscx82525
    Text: LAPB/LAPD controlling machine providing − modulo 8 frame numbering HDLC − modulo 128 frame numbering HDLC Protocol Controller Core − automatically generated res- − one- or two-byte addressing ponses Serial Peripheral Interfaces − Bit stuffing The HDLC core implements a single- or dual-channel controller for the High-Level Data


    Original     		PDF

    PT7A6525

    Abstract: PT7A6525J PT7A6525LJ PT7A6525L mc 6526 p pt7a6526je PT7A6525M PT7A6525LJE CD 1517 PT7A65
    Text: Data Sheet PT7A6525/6525L/6526 HDLC Controller |


    Original     		PDF PT7A6525/6525L/6526 PT7A6526: modulo-128 PT0017 PT7A6525 PT7A6525J PT7A6525LJ PT7A6525L mc 6526 p pt7a6526je PT7A6525M PT7A6525LJE CD 1517 PT7A65

    mc 6526 p

    Abstract: PT7A6525 motorola 6526
    Text: Data Sheet PT7A6525/6525L/6526 HDLC Controller |


    Original     		PDF PT7A6525/6525L/6526 PT7A6526: modulo-128 PT7A6525/6525L: PT0017 mc 6526 p PT7A6525 motorola 6526

    TP31C

    Abstract: DS3131 DS3134 LA10 LA12 TD39 811B
    Text: DALLAS SEMICONDUCTOR DS3131 Preliminary Data Sheet V2 January 26, 1999 DALLAS SEMICONDUCTOR DS3131 BoSS Bit SynchronouS HDLC CONTROLLER 40 Port / 40 Channel HDLC Controller with Option for Local Bus Access Preliminary Data Sheet Version 2 January 26, 1999


    Original     		PDF DS3131 DS3131 164Mbps 132Mbps. 50MHz 33MHz. DS3131. TP31C DS3134 LA10 LA12 TD39 811B

    HDLC verilog code

    Abstract: testbench verilog ram 16 x 8 crc verilog code 16 bit VERILOG CODE FOR HDLC controller hdlc R8051XC verilog code of 16 bit comparator R8051XC-HDLC
    Text:  LAPB/LAPD controlling machine providing  modulo 8 frame numbering HDLC  modulo 128 frame numbering HDLC Protocol Controller Core  automatically generated res-  one- or two-byte addressing ponses  Serial Peripheral Interfaces  Bit stuffing


    Original     		PDF

    HSCX 82525

    Abstract: R8051XC-HDLC hdlc R8051XC
    Text:  LAPB/LAPD controlling machine providing  modulo 8 frame numbering HDLC  modulo 128 frame numbering HDLC Protocol Controller Megafunction  automatically generated res-  one- or two-byte addressing ponses  Serial Peripheral Interfaces  Bit stuffing


    Original     		PDF R8051XC R8051XC HSCX 82525 R8051XC-HDLC hdlc

    TP31C

    Abstract: PCI Backplane DS3131 DS3134 TC10 TC12 TD39 811af 32 bit pci backplane LD0-TC28
    Text: DS3131 BoSS Bit SynchronouS HDLC Controller www.dalsemi.com FEATURES • • • • • • • • • • • 40 timing independent bit synchronous ports 40Rx & 40Tx coupled with 40 independent Bi-directional HDLC channels Each port can operate up to 52 Mbps


    Original     		PDF DS3131 32-bit DS3131 DS3131. TP31C PCI Backplane DS3134 TC10 TC12 TD39 811af 32 bit pci backplane LD0-TC28

    CD 40818 BE

    Abstract: capacitor PMR 202 DM preset 103 CD4400 ARM7 ISA RW185 40818 SPC3 st c transistor 40410 CL-CD4400s
    Text: CL-CD4400 'CIRRUSIDG/C Advance Data Book FEATURES • Four full-duplex, multi-protocol serial channels ■ All channels support async-HDLC/PPP, async, HDLC, or programmable sync ■ Sync bit rates up to 8 Mbits/sec. on all channels; up to 52 Mbits/sec. on a single channel in HDLC or


    OCR Scan     		PDF CL-CD4400 inte83 CD 40818 BE capacitor PMR 202 DM preset 103 CD4400 ARM7 ISA RW185 40818 SPC3 st c transistor 40410 CL-CD4400s

    8273 dma controller

    Abstract: Intel 8080 interface Intel 8080 CPU Diagram intel 8085 clock 8085 intel SDLC PROTOCOL intel 8273 8273
    Text: in te 1 8273 PROGRAMMABLE HDLC/SDLC PROTOCOL CONTROLLER CCITT X.25 Compatible Programmable NRZI Encode/Decode HDLC/SDLC Compatible Two Programmable Modem Control Ports Full Duplex, Half Duplex, or Loop SDLC Operation Digital Phase Locked Loop Clock Recovery


    OCR Scan     		PDF 21047M 8273 dma controller Intel 8080 interface Intel 8080 CPU Diagram intel 8085 clock 8085 intel SDLC PROTOCOL intel 8273 8273

    8086 8257 DMA controller interfacing

    Abstract: interfacing of 8257 with 8086 IC KD 2107 6 PIN 8257 DMA controller intel DMA controller Unit for 80186 8273 dma controller interfacing of 8257 devices with 8085 i8273
    Text: in te i 8273 PROGRAMMABLE HDLC/SDLC PROTOCOL CONTROLLER CCITT X.25 Compatible Programmable NRZI Encode/Decode HDLC/SDLC Compatible Two Programmable Modem Control Ports Full Duplex, Half Duplex, or Loop SDLC Operation Digital Phase Locked Loop Clock Recovery


    OCR Scan     		PDF

    8086 8257 DMA controller interfacing

    Abstract: interfacing of 8257 with 8086 intel 8257 interrupt controller GA27-3093 Intel 8257 intel d 8273 intel 8273 8273 dma controller 8086 8257 DMA controller MCS-80
    Text: in te i 8273 PROGRAMMABLE HDLC/SDLC PROTOCOL CONTROLLER CCITT X.25 Compatible Programmable NRZI Encode/Decode HDLC/SDLC Compatible Two Programmable Modem Control Ports Full Duplex, Half Duplex, or Loop SDLC Operation Digital Phase Locked Loop Clock Recovery


    OCR Scan     		PDF

    Intel 8080 CPU Diagram

    Abstract: intel 8273 IBM 8080 Intel 8080 block Diagram intel 8085 a hdlc sdlc chip intel 8080 architecture intel 8085 MCS intel 8080 MCS intel 8085 clock
    Text: in le l 8273 PROGRAMMABLE HDLC/SDLC PROTOCOL CONTROLLER CCITT X.25 Compatible Programmable NRZI Encode/Decode HDLC/SDLC Compatible Two Programmable Modem Control Ports Full Duplex, Half Duplex, or Loop SDLC Operation Up to 64K Baud Synchronous Transfers Automatic FCS CRC Generation and


    OCR Scan     		PDF

    8086 8257 DMA controller interfacing

    Abstract: interfacing of 8257 with 8086 8273 dma controller interfacing of 8257 devices with 8085 8086 8257 DMA controller intel 8257 intel 8080 architecture intel 8273 GA27-3093 8228 DI
    Text: in t e i 8273, 8273-4, 8273-8 PROGRAMMABLE HDLC/SDLC PROTOCOL CONTROLLER • CCITT X.25 Compatible ■ Programmable NRZI Encode/Decode ■ HDLC/SDLC Compatible ■ Two User Programmable Modem Control Ports ■ Full Duplex, Half Duplex, or Loop SDLC Operation


    OCR Scan     		PDF 150pF AFN-00743B AFN-00743B 8086 8257 DMA controller interfacing interfacing of 8257 with 8086 8273 dma controller interfacing of 8257 devices with 8085 8086 8257 DMA controller intel 8257 intel 8080 architecture intel 8273 GA27-3093 8228 DI

    Untitled

    Abstract: No abstract text available
    Text: DALLAS SEMICONDUCTOR DS3131 Preliminary Data Sheet V2 January 26, 1999 DALLAS SEMICONDUCTOR DS3131 BoSS Bit Synchronous HDLC CONTROLLER 40 Port / 40 Channel HDLC Controller with Option for Local Bus Access Preliminary Data Sheet Version 2 January 26, 1999


    OCR Scan     		PDF DS3131 DS3131 164Mbps 132Mbps. 50MHz 33MHz. DS3131.

    TP31C

    Abstract: r02f Boss NS-2 PAB1 td33 LDO DS3131 DS3134 LA10 LA12 TD39
    Text: DALLAS SEM ICONDUCTOR DS3131 Preliminary Data Sheet V2 January 26, 1999 DALLAS SEMICONDUCTOR DS3131 BoSS Bit Synchronous HDLC CONTROLLER 40 Port / 40 Channel HDLC Controller with Option for Local Bus Access Preliminary Data Sheet Version 2 January 26, 1999


    OCR Scan     		PDF DS3131 164Mbps 132Mbps. 50MHz 33MHz. DS3131. TP31C r02f Boss NS-2 PAB1 td33 LDO DS3134 LA10 LA12 TD39

    Untitled

    Abstract: No abstract text available
    Text: DALLAS SEM ICONDUCTOR DS3131 Preliminary Data Sheet V1 August 6, 1998 DALLAS SEMICONDUCTOR DS3131 BOSS Bit and Octet Synchronous HDLC CONTROLLER 40 Port / 40 Channel HDLC Controller with Options for Local Bus Access & an Octet Synchronous Port Preliminary Data Sheet


    OCR Scan     		PDF DS3131 DS3131 DS3131.

    RFC-1331

    Abstract: CL-CD2431
    Text: CL-CD2430ICD2431 DataBook 'CIRRUS LOGIC FEATURES • Four full-duplex multi-protocol channels, each running up to 128 kbits/second ■ Supports async, async-HDLC high-level data link control , and HDLC/SDLC (synchronous data link control) on all channels


    OCR Scan     		PDF CL-CD2430ICD2431 CL-CD2430 CL-CD2431 84-pin CL-CD2401 1287b RFC-1331