hdlc
Abstract: 806C MC68360
Text: MOTOROLA SEMICONDUCTOR TECHNICAL INFORMATION Asynchronous HDLC MC68360 ASYNC HDLC Protocol Microcode User’s Manual Rev 1.1 January 24, 1996 Asynchronous HDLC Asynchronous HDLC 1 ASYNC HDLC Controller Overview 4 2 ASYNC HDLC Controller Key Features 2.1 ASYNC HDLC Channel Frame Transmission Processing
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MC68360
hdlc
806C
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hdlc
Abstract: IEC3309 XF-HDLC RFC1619 XC4000XL HDLC controller CC318f
Text: HDLC Controller Solutions with Spartan-II FPGAs Customer Tutorial February 2000 File Number Here Agenda Introduction HDLC Overview HDLC Controller Applications Spartan-II IP Solutions for HDLC Controllers HDLC Controller ASSPs Spartan-II Family - Programmable ASSP
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2RD6
Abstract: RB35 TDNB0
Text: BACK HDLC Device HDLC Controller TXC-05101C DATA SHEET Preliminary FEATURES DESCRIPTION • HDLC ISO/OSI level 2 functions, including internal flag, abort, and zero deletion/insertion The TranSwitch TXC-05101C is a high speed, High Level Data Link Controller HDLC designed to send
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TXC-05101C
CRC-16
CRC-32
36-bit
TXC-05101C-MB
2RD6
RB35
TDNB0
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RB35
Abstract: TB28 hdlc CRC16 CRC-16 CRC-32 TB31 TB32 RXB 17-18
Text: HDLC Device HDLC Controller TXC-05101C DATA SHEET Preliminary FEATURES DESCRIPTION • HDLC ISO/OSI level 2 functions, including internal flag, abort, and zero deletion/insertion The TranSwitch TXC-05101C is a high speed, High Level Data Link Controller HDLC designed to send
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TXC-05101C
TXC-05101C
TXC-05101C-MB
RB35
TB28
hdlc
CRC16
CRC-16
CRC-32
TB31
TB32
RXB 17-18
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PDF
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hdlc
Abstract: No abstract text available
Text: Am186 CC-Based Low-End Router Reference Design TM DRAM Flash SRAM Memory Controller WAN via ISDN Transformer Transceiver Am79C32A G C I Am186CC HDLC HDLC HDLC HDLC PCM SSI DSLAC RSLIC POTS RSLIC B I U Ethernet Ethernet Am79C961A LAN (Ethernet)
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Am186
Am79C32A
Am186CC
Am79C961A
hdlc
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Cyclic Redundancy Check simulation
Abstract: CRC-16 and verilog crc 16 verilog design of dma controller using vhdl
Text: HDLC Functions FPGA/CPLD IP D TX_CRC_ERR HDLC_EN CRC_16 TX_CLK RX_CLK RST Inventra HDLC-CORE-B1 Single Channel HDLC Core A T A S H E E T HDLC-CORE key features: • HDLC processor • Flag generation & detection RX/TX CONTROL RX_DATA_OCTET TX_DATA_OCTET
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32-bit
PD-32302
001-FO
Cyclic Redundancy Check simulation
CRC-16 and verilog
crc 16 verilog
design of dma controller using vhdl
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PDF
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gapped
Abstract: AN392 APP392 DS31256 TS24 E1 frame
Text: Maxim > App Notes > TELECOM Keywords: gapped clock, hdlc controller, HDLC Nov 21, 2002 APPLICATION NOTE 392 DS31256 Gapped Clock Applications Abstract: This application note discusses how to realize gapped clock applications with the DS31256 HDLC Controller.
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DS31256
DS31256.
DS31256,
256-channel
com/an392
DS31256:
AN392,
gapped
AN392
APP392
TS24
E1 frame
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Bi-phase-L Coding
Abstract: CRC16 D555 MPC821 manchester differential
Text: Communication Processor Module 16.14 SERIAL COMMUNICATION CONTROLLERS The following is a list of the SCCs’ important features: • Implements HDLC/SDLC, HDLC bus, asynchronous HDLC, BISYNC, synchronous start/stop, asynchronous start/stop UART , AppleTalk/LocalTalk, and totally
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10-Mbps
MPC821
Bi-phase-L Coding
CRC16
D555
manchester differential
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PDF
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Untitled
Abstract: No abstract text available
Text: HDLC Evaluation Board 36-Bit HDLC Terminal TXC-21043 PRODUCT INFORMATION FEATURES DESCRIPTION • Complete test fixture for evaluation of the TranSwitch HDLC TXC-05101 device A complete ready-to-use single-board test system that demonstrates the functions and features of the TranSwitch HDLC
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36-Bit
TXC-21043
TXC-05101)
RS-232
TXC-21043-AAAA
TXC-21043-MC
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PDF
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hdlc
Abstract: 08FF DS31256 AN307
Text: Maxim > App Notes > TELECOM Feb 26, 2004 Keywords: hdlc controller, test registers, HDLC, controllers APPLICATION NOTE 3071 Internal Test Registers for the DS31256 Abstract: This application note lists the internal test registers in DS31256 HDLC Controller, and explains why
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DS31256
DS31256
com/an3071
DS31256:
AN3071,
APP3071,
Appnote3071,
hdlc
08FF
AN307
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Untitled
Abstract: No abstract text available
Text: HDLC Controllers TELEPHONY/PRIMARY RATE TRANSMISSION T1, E1, J1 VOICE/DATA Features Packaging www.ZARLINK.com 5.0V 3.3V 8.192 Mbps 19 Fixed 1 Backplane Floating FIFO depth (KB) JTAG # of HDLC MT8952 Loopback modes J1 E1 T1 # of framers HDLC 2.048 Mbps Part #
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MT8952
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AN3345
Abstract: APP3345 hdlc DS21FF42 DS21FT42 DS21Q55 DS26528 DS3112 DS31256 DS3150
Text: Maxim/Dallas > App Notes > TELECOM Keywords: HDLC controller, framer, transceiver, T1/E1, T3/E3, hdlc, controller, t1, e1, t3, e3 Sep 09, 2004 APPLICATION NOTE 3345 Examples of DS31256 Applications App Note 3345 provides application examples for the DS31256 HDLC Controller.
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DS31256
DS31256,
DS21FF42:
DS21FT42:
DS21Q55:
DS26528:
DS3112:
DS31256:
AN3345
APP3345
hdlc
DS21FF42
DS21FT42
DS21Q55
DS26528
DS3112
DS3150
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HDLC
Abstract: No abstract text available
Text: Am186 CH HDLC Microcontroller TM The Am186 CH HDLC microcontroller is a subset of the Am186CC communications controller. It was developed for customers who require HDLC channels, but no USB controller. Specifically, it provides a cost reduced alternative to the
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Am186
Am186CC
Am186CH
Comm86TM
Am186TM
Am186CC/CH/CU
HDLC
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MPC821
Abstract: No abstract text available
Text: Communication Processor Module 16.14.19.2 ASYNC HDLC CHANNEL FRAME TRANSMISSION PROCESSING. The ASYNC HDLC controller is designed to work with a minimum amount of intervention from the CPU core. It operates in a similar fashion to the HDLC controller on the MPC821.
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MPC821.
MPC821
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TH21C
Abstract: TP31C hdlc 11-B DS3131 TD39
Text: DEMO KIT AVAILABLE DS3131 BoSS 40-Port, Unchannelized Bit-Synchronous HDLC www.maxim-ic.com GENERAL DESCRIPTION FEATURES The DS3131 bit-synchronous BoSS HDLC controller can handle up to 40 channels of highspeed, unchannelized, bit-synchronous HDLC. The on-board DMA has been optimized for
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DS3131
40-Port,
DS3131
DS3131.
TH21C
TP31C
hdlc
11-B
TD39
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rc16 8pin
Abstract: DS3131 DS3131DK LT1086 TD39 la6 dk RC39
Text: DS3131DK Bit-SynchronouS BoSS HDLC Controller Demo Kit www.maxim-ic.com GENERAL DESCRIPTION FEATURES § § § § § § § § § The DS3131 bit-synchronous (BoSS) HDLC controller can handle up to 40 channels of highspeed, unchannelized, bit-synchronous HDLC.
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DS3131DK
DS3131
52Mbps
132Mbps
DS3134
rc16 8pin
DS3131DK
LT1086
TD39
la6 dk
RC39
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HDLC 3309 1993
Abstract: DS3134 RS15 TD15 TS15 33091
Text: PRELIMINARY DS3134 Chateau – Channelized T1 And E1 And HDLC Controller www.dalsemi.com FEATURES • • • • • • • • • • 256 Channel HDLC Controller that Supports up to 64 T1 or E1 Lines or Two T3 Lines 256 Independent bi-directional HDLC
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DS3134
DS21FF42
DS21FT42
HDLC 3309 1993
DS3134
RS15
TD15
TS15
33091
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PDF
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hdlc
Abstract: ITA03968 MUNICH32 80386 microprocessor block diagram Motorola 68020 "network interface controller"
Text: Multichannel Network Interface Controller for HDLC MUNICH32 PEB 20320 General Description The Multichannel Network Interface Controller for HDLC (MUNICH32, PEB 20320) is a multichannel protocol controller which handles up to 32 data channels of a fullduplex PCM highway. It performs layer-2 HDLC formatting/
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MUNICH32)
20320-H
P-MQFP-160-1
80-bit
ITA03968
hdlc
ITA03968
MUNICH32
80386 microprocessor block diagram
Motorola 68020
"network interface controller"
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VHDL CODE FOR HDLC controller
Abstract: VHDL CODE FOR HDLC vhdl code for pcm bit stream generator slot machine block diagram vhdl
Text: Multi-Channel HDLC Controller with PCI Interface Today, there is a variety of HDLC controller chips available from companies like Rockwell Semiconductor, PMC-Sierra and Siemens. Additionally, microprocessors from Motorola and AMD integrate HDLC controllers onchip. These solutions strive to offer flexibility and high
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16-bit
1-800-LATTICE
VHDL CODE FOR HDLC controller
VHDL CODE FOR HDLC
vhdl code for pcm bit stream generator
slot machine block diagram vhdl
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TP31C
Abstract: 083C Cables datasheet rh16c RH25CR hdlc 11-B DS3131 TD39 TH21C rbp2
Text: DEMO KIT AVAILABLE DS3131 BoSS 40-Port, Unchannelized Bit-Synchronous HDLC www.maxim-ic.com GENERAL DESCRIPTION FEATURES The DS3131 bit-synchronous BoSS HDLC controller can handle up to 40 channels of highspeed, unchannelized, bit-synchronous HDLC. The on-board DMA has been optimized for
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DS3131
40-Port,
DS3131
DS3131.
TP31C
083C Cables datasheet
rh16c
RH25CR
hdlc
11-B
TD39
TH21C
rbp2
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0X008H
Abstract: No abstract text available
Text: PRELIMINARY DS3134 Chateau – Channelized T1 And E1 And HDLC Controller www.dalsemi.com FEATURES • • • • • • • • • • 256 Channel HDLC Controller that Supports up to 64 T1 or E1 Lines or Two T3 Lines 256 Independent bi-directional HDLC
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DS3134
DS21FF42
DS21FT42
0X008H
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AN2872
Abstract: hdlc 070C 071C APP2872 DS31256 0x10002000 "watermark"
Text: Maxim > App Notes > T/E Carrier and Packetized Keywords: DS31256, HDLC controller, bridge mode, Dec 04, 2003 APPLICATION NOTE 2872 DS31256 HDLC Controller Step-by-Step Configuration—Bridge Mode Abstract: This application note provides an example of how to configure a single T1 port on DS31256 HDLC
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DS31256,
DS31256
DS31256:
com/an2872
AN2872,
APP2872,
Appnote2872,
AN2872
hdlc
070C
071C
APP2872
0x10002000
"watermark"
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processor 80386
Abstract: Motorola 68020 "network interface controller"
Text: Multichannel Network Interface Controller for HDLC MUNICH32 General Description The Multichannel Network Interface Controller for HDLC (MUNICH32, PEB 20320) is a multichannel protocol controller which handles up to 32 data channels of a fullduplex PCM highway. It performs layer-2 HDLC formatting/
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MUNICH32)
MUNICH32,
MUNICH32
processor 80386
Motorola 68020
"network interface controller"
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PDF
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B15C
Abstract: d0415 TB-33 RB35
Text: HDLC Device HDLC Controller, 36-bit Terminal I/O TXC-05101 DATA SHEET Preliminary . FEATURES = = = = = ¿ ^ - 1 - -— DESCRIPTION = • HDLC ISO/OSI level 2 functions, including internal flag, abort, and zero deletion/insertion • Operates up to 51.84 Mbit/s STS-1 data rates
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36-bit
TXC-05101
CRC-16
CRC-32
TXC-05101
B15C
d0415
TB-33
RB35
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