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    HD74HC10 Search Results

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    HD74HC10 Price and Stock

    Rochester Electronics LLC HD74HC10PD

    IC GATE NAND 3CH 3-INP
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    DigiKey HD74HC10PD Bulk 378
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    Renesas Electronics Corporation HD74HC10PD

    HD74HC10PD
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    Verical HD74HC10PD 3,000 418
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    Rochester Electronics HD74HC10PD 3,000 1
    • 1 $0.7644
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    Hitachi Ltd HD74HC10P

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    Bristol Electronics HD74HC10P 5,157
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    Quest Components HD74HC10P 4,125
    • 1 $0.7
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    HD74HC10P 20
    • 1 $6
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    Renesas Electronics Corporation HD74HC10FPEL

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    Quest Components HD74HC10FPEL 1,524
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    HD74HC10 Datasheets (46)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    HD74HC10 Hitachi Semiconductor Triple 3-input NAND Gates Original PDF
    HD74HC10 Renesas Technology Triple 3-input NAND Gates Original PDF
    HD74HC10 Renesas Technology Original PDF
    HD74HC107 Hitachi Semiconductor Dual J-K Flip-Flops (with Clear) Original PDF
    HD74HC107 Renesas Technology Dual J-K Flip-Flops (with Clear) Original PDF
    HD74HC107FP Hitachi Semiconductor Flip-Flop, Negative-Edge, JK Flip-Flop, 2-Element, 2-Input, 14-SOP Original PDF
    HD74HC107FP Renesas Technology Dual J-K Flip-Flops with Clear Original PDF
    HD74HC107FP Renesas Technology Logic IC; Function: Dual J-K Flip-Flops with Clear; Package: SOP Original PDF
    HD74HC107P Hitachi Semiconductor Flip-Flop, Negative-Edge, JK Flip-Flop, 2-Element, 2-Input, 14-DIP Original PDF
    HD74HC107P Renesas Technology Dual J-K Flip-Flops with Clear Original PDF
    HD74HC107RP Hitachi Semiconductor Flip-Flop, Negative-Edge, JK Flip-Flop, 2-Element, 2-Input, 14-SOP Original PDF
    HD74HC107RP Renesas Technology Dual J-K Flip-Flops with Clear Original PDF
    HD74HC107T Renesas Technology Flip Flop, Dual J-K Flip-Flops (with Clear) Original PDF
    HD74HC108 Hitachi Semiconductor Dual J-K Flip-Flops (with Preset, Common Clear and Common Clock) Original PDF
    HD74HC108 Renesas Technology Dual J-K Flip-Flops (with Preset, Common Clear and Common Clock) Original PDF
    HD74HC108FP Hitachi Semiconductor Flip-Flop, Negative-Edge, JK Flip-Flop, 2-Element, 2-Input, 14-SOP Original PDF
    HD74HC108FP Renesas Technology Dual J-K Flip-Flops with Preset, Common Clear, Common Clock Original PDF
    HD74HC108P Hitachi Semiconductor Flip-Flop, Negative-Edge, JK Flip-Flop, 2-Element, 2-Input, 14-DIP Original PDF
    HD74HC108P Renesas Technology Logic Gate, Dual J-K Flip-Flops (with Preset, Common Clear and Common Clock) Original PDF
    HD74HC108RP Hitachi Semiconductor Flip-Flop, Negative-Edge, JK Flip-Flop, 2-Element, 2-Input, 14-SOP Original PDF

    HD74HC10 Datasheets Context Search

    Catalog Datasheet MFG & Type Document Tags PDF

    HD74HC107

    Abstract: Hitachi DSA00279
    Text: HD74HC107 Dual J-K Flip-Flops with Clear Description This flip-flop is edge sensitive to the clock input and change state on the negative going transition of the clock pulse. Each one has independent J, K, clock, and clear inputs and Q and Q outputs. Clear is


    Original     		HD74HC107 HD74HC107 Hitachi DSA00279 PDF

    HD74HC107

    Abstract: HD74HC107P HD74HC107FPEL PRDP0014AB-B PRSP0014DF-B
    Text: HD74HC107 Dual J-K Flip-Flops with Clear REJ03D0559-0200 (Previous ADE-205-432) Rev.2.00 Oct 06, 2005 Description This flip-flop is edge sensitive to the clock input and change state on the negative going transition of the clock pulse. Each one has independent J, K, clock, and clear inputs and Q and Q outputs. Clear is independent of the clock and


    Original     		HD74HC107 REJ03D0559-0200 ADE-205-432) HD74HC107P HD74HC107 HD74HC107P HD74HC107FPEL PRDP0014AB-B PRSP0014DF-B PDF

    DP-14

    Abstract: FP-14DA FP-14DN HD74HC108 TTP-14D Hitachi DSA00395
    Text: HD74HC108 Dual J-K Flip-Flops with Preset, Common Clear and Common Clock Description This flip-flop is edge sensitive to the clock input and change state on the negative transition of the clock pulse. Each flip-flop has independent J, K, and preset inputs and Q and Q outputs. Two flip-flops are


    Original     		HD74HC108 DP-14 FP-14DA FP-14DN HD74HC108 TTP-14D Hitachi DSA00395 PDF

    HD74HC109

    Abstract: Hitachi DSA00396
    Text: HD74HC109 Dual J-K Flip-Flops with Preset and Clear Description Each flip-flop has independent J, K, preset, clear and clock inputs and Q and Q outputs. This device is edge sensitive to the clock input and changes state on the positive going transition of the clock pulse. Clear


    Original     		HD74HC109 HD74HC109 Hitachi DSA00396 PDF

    506 K 7 20 7

    Abstract: HD74HC109 Hitachi DSA00221
    Text: HD74HC109 Dual J-K Flip-Flops with Preset and Clear ADE-205-434 (Z) 1st. Edition Sep. 2000 Description Each flip-flop has independent J, K, preset, clear and clock inputs and Q and Q outputs. This device is edge sensitive to the clock input and changes state on the positive going transition of the clock pulse. Clear


    Original     		HD74HC109 ADE-205-434 506 K 7 20 7 HD74HC109 Hitachi DSA00221 PDF

    Hitachi DSA00279

    Abstract: No abstract text available
    Text: HD74HC109 Dual J-K Flip-Flops with Preset and Clear Description Each flip-flop has independent J, K, preset, clear and clock inputs and Q and Q outputs. This device is edge sensitive to the clock input and changes state on the positive going transition of the clock pulse.


    Original     		HD74HC109 Hitachi DSA00279 PDF

    HD74HC10

    Abstract: Hitachi DSA0095 DP-14 FP-14DA FP-14DN TTP-14D
    Text: HD74HC10 Triple 3-input NAND Gates ADE-205-410 Z 1st. Edition Sep. 2000 Features • • • • • High Speed Operation: tpd = 10.5 ns typ (CL = 50 pF) High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 µA max


    Original     		HD74HC10 ADE-205-410 HD74HC10 Hitachi DSA0095 DP-14 FP-14DA FP-14DN TTP-14D PDF

    DP-14

    Abstract: FP-14DA FP-14DN HD74HC107 TTP-14D Hitachi DSA00395
    Text: HD74HC107 Dual J-K Flip-Flops with Clear Description This flip-flop is edge sensitive to the clock input and change state on the negative going transition of the clock pulse. Each one has independent J, K, clock, and clear inputs and Q and Q outputs. Clear is


    Original     		HD74HC107 DP-14 FP-14DA FP-14DN HD74HC107 TTP-14D Hitachi DSA00395 PDF

    HD74HC109

    Abstract: HD74HC109FPEL HD74HC109P HD74HC109RPEL PRDP0016AE-B PRSP0016DH-B
    Text: HD74HC109 Dual J-K Flip-Flops with Preset and Clear REJ03D0561-0200 (Previous ADE-205-434) Rev.2.00 Oct 11, 2005 Description Each flip-flop has independent J, K, preset, clear and clock inputs and Q and Q outputs. This device is edge sensitive to the clock input and changes state on the positive going transition of the clock pulse. Clear and preset are independent of


    Original     		HD74HC109 REJ03D0561-0200 ADE-205-434) HD74HC109 HD74HC109FPEL HD74HC109P HD74HC109RPEL PRDP0016AE-B PRSP0016DH-B PDF

    HD74HC108

    Abstract: PRSP0014DE-A
    Text: HD74HC108 Dual J-K Flip-Flops with Preset, Common Clear and Common Clock REJ03D0560-0200 (Previous ADE-205-433) Rev.2.00 Oct 11, 2005 Description This flip-flop is edge sensitive to the clock input and change state on the negative transition of the clock pulse. Each


    Original     		HD74HC108 REJ03D0560-0200 ADE-205-433) HD74HC108 PRSP0014DE-A PDF

    HD74HC107

    Abstract: DP-14 FP-14DA FP-14DN Hitachi DSA00221
    Text: HD74HC107 Dual J-K Flip-Flops with Clear ADE-205-432 (Z) 1st. Edition Sep. 2000 Description This flip-flop is edge sensitive to the clock input and change state on the negative going transition of the clock pulse. Each one has independent J, K, clock, and clear inputs and Q and Q outputs. Clear is


    Original     		HD74HC107 ADE-205-432 HD74HC107 DP-14 FP-14DA FP-14DN Hitachi DSA00221 PDF

    Untitled

    Abstract: No abstract text available
    Text: Ì5 HITACHI/ LOGIC/ARRAYS/MEM DE] 4 4 ^ 5 0 3 0GlD3b3 92D HD74HC107 4 |~ V T ~ lf b ~ '0 7 - '0 7 10363 Dual J-K Flip-Flops with Clear This flip-flop is edge sensitive to the clock input and change | PIN ARRANGEMENT state on the negative going transition of the clock pulse.


    OCR Scan     		HD74HC107 0D1D315 T-90-20 PDF

    R16-14

    Abstract: No abstract text available
    Text: HD74HC107 # Dual J-K Flip-Flops with Clear This flip -flo p is edge sensitive to the clock input and change | PIN ARRANGEMENT state on the negative going transition of the clock pulse. Each one has independent J, K, clock, and clear inputs and Q and Q outputs. Clear is independent of the clock and


    OCR Scan     		HD74HC107 R16-14 PDF

    Untitled

    Abstract: No abstract text available
    Text: HD74HC108 # Dual J-K Flip-Flops with Preset, Common Clear, and Common Clock This flip-flop is edge sensitive to the clock input and change state on the negative transition of the clock pulse. Each PIN ARRANGMENT flip-flop has independent J, K, and preset inputs and Q and


    OCR Scan     		HD74HC108 PDF

    Untitled

    Abstract: No abstract text available
    Text: HD74HC108 Dual J-K Flip-Flops w ith Preset, Com m on C lear, a n d Common C lock # This flip-flop it edge sensitive to the clock input and change state on the negative transition of the clock pulse. Each flip-flop h a t independent J, K, and preset input« and Q and


    OCR Scan     		HD74HC108 PDF

    Untitled

    Abstract: No abstract text available
    Text: HD74HC107 Dual J-K Flip-Flops with Clear This flip-flop is edge sensitive to the clock input and change | PIN ARRANGEMENT state on the negative going transition of the clock pulse. Each one has independent J, K, clock, and clear inputs and Q and Q outputs. Clear is independent of the clock and


    OCR Scan     		HD74HC107 PDF

    Untitled

    Abstract: No abstract text available
    Text: HITACHI/ LOGIC/ARRAYS/flEM ~T5 D Ë J 441t,5G3 GDlGBb? 1 | ~ 92 D HD74HC109 # 10367 Dual J-K Flip-Flops with Preset and Clear Each flip-flop has independent J, K, preset, clear and clock | PIN ARRA N G EM EN T inputs and Q and Q outputs. This device is edge sensitive to


    OCR Scan     		HD74HC109 0D1D315 T-90-20 PDF

    Untitled

    Abstract: No abstract text available
    Text: HD74HC109 # Dual J-K Flip-Flops with Preset and Clear Each flip -flo p has independent J, K, preset, clear and clock | inputs and Q and Q outputs. This device is edge sensitive to PIN ARRANGEMENT ~ \y ~ Vcc the clock input and changes state on the positive going


    OCR Scan     		HD74HC109 PDF

    Untitled

    Abstract: No abstract text available
    Text: HD74HC109 # Oual J-R Fhp-Flops with Preset and Clear Each flip-flop ha* in d e p e n d e n t j , K, preset, clear and clock Input* and Q and Q outputs. This device it edge sensitive to the dock input and change« «ate on the positive going transition of the dock pulse. Clear and preset are indepen­


    OCR Scan     		HD74HC109 Ta--40~ PDF

    Untitled

    Abstract: No abstract text available
    Text: HD74HC10 • Triple 3-input NAND Gates • FEATURES I PIN ARRANGEMENT • High Speed Operation: \p d = 10.5ns typ. Q _=50pF • High Output Current: Fanout of 10 LSTTL Loads • Wide Operating Voltage: Vcc = 2 ~ 6V • Low Input Current: 1jjA max. • Low Quiescent Supply Current:/cc (static) = 1;uA max. (Ta = 25°C)


    OCR Scan     		HD74HC10 20//A --40---h85 PDF

    Untitled

    Abstract: No abstract text available
    Text: HD74HC109 « d»* J-K Flip-Flops with Preset and Clear Each flip-flop has independent J, K, preset, clear and clock inputs and Q and Q outputs. This device is edge sensitive to the dock input and changes state on the positive going transition of the d ock pulse. Clear and preset are indepen­


    OCR Scan     		HD74HC109 PDF

    Untitled

    Abstract: No abstract text available
    Text: H ITA C H I/ LOGIC/ARRAYS/MEN TE D Ë | 44i h a D 3 DülDBbS 92D HD74HC108 10365 fl D Dual J-K Flip-Flops with Preset Common Clear, and Common Clock PIN ARRANGMENT T h is flip -flo p is edge sensitive to the clo c k in p u t and change state o n the negative tran sition o f the clo c k pulse. Each


    OCR Scan     		HD74HC108 0D1D315 T-90-20 PDF

    Untitled

    Abstract: No abstract text available
    Text: HD74HC10 • Triple 3-input HAND Gates • FEATURES • • • • • | PIN ARRANGEMENT High Speed Operation: tprf-IO.&n* typ. C^ -50pF High Output Currant: Fanout of 10 LSTTL Load* Wide Operating Voltage l/cc-2~6V Low Input Currant: 1j»A max. Low Quiescent Supply Currant: Icc (static) - 1/iA max. (r»«2B°CI


    OCR Scan     		HD74HC10 -50pF) --20/iA PDF

    Untitled

    Abstract: No abstract text available
    Text: HD74HC107 • Dual J-K Flip-Flops with Clear This flip-flop is edge sensitive to the dock Input and change state on the negative going transition of the clock pulse. Each one hat independent J, K, dock, and dear inputs and Q and Q outputs. Clear It independent of the clock and


    OCR Scan     		HD74HC107 7a-25 PDF