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Nexperia 74LV1T126GXH Translation - Voltage Levels 74LV1T126GX/SOT1226/X2SON5
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
Mouser Electronics	74LV1T126GXH		118,691			1 $0.31 10 $0.226 100 $0.161 1000 $0.107 10000 $0.087	Buy Now
Nexperia 74LV1T32GXH Translation - Voltage Levels 74LV1T32GX/SOT1226/X2SON5
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Mouser Electronics	74LV1T32GXH		45,344			1 $0.27 10 $0.188 100 $0.106 1000 $0.096 10000 $0.09	Buy Now
Nexperia 74LV1T08GXH Translation - Voltage Levels 74LV1T08GX/SOT1226/X2SON5
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Mouser Electronics	74LV1T08GXH		32,129			1 $0.35 10 $0.286 100 $0.195 1000 $0.107 10000 $0.087	Buy Now
Nexperia 74LVC1G14GX4-Q100Z Inverters 74LVC1G14GX4-Q100/SOT1269/X2SO
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
Mouser Electronics	74LVC1G14GX4-Q100Z		28,911			1 $0.42 10 $0.311 100 $0.21 1000 $0.131 10000 $0.104	Buy Now
Nexperia 74AUP1G14GX4-Q100Z Inverters 74AUP1G14GX4-Q100/SOT1269/X2SO
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
Mouser Electronics	74AUP1G14GX4-Q100Z		24,530			1 $0.42 10 $0.311 100 $0.199 1000 $0.131 10000 $0.109	Buy Now

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GX 717 Datasheets Context Search

Catalog Datasheet	MFG & Type	PDF	Document Tags
circuit diagram of inverting adder Abstract: KR 108 6621 3.3V Text: Stratix GX FPGA Family Data Sheet December 2004, ver. 2.2 Introduction The Stratix GX family of devices is Altera’s second FPGA family to combine high-speed serial transceivers with a scalable, high-performance logic array. Stratix GX devices include 4 to 20 high-speed transceiver	Original	PDF
EP1SGX25CF672C7 Abstract: No abstract text available Text: Stratix GX FPGA Family Data Sheet February 2004, ver. 2.1 Introduction The Stratix GX family of devices is Altera's second FPGA family to combine high-speed serial transceivers with a scalable, high-performance logic array. Stratix GX devices include 4 to 20 high-speed transceiver	Original	PDF	EP1SGX25C 125-Gbps EP1SGX25CF672C5 EP1SGX25CF672C6 EP1SGX25CF672C7 EP1SGX25C EP1SGX25CF672C7
Untitled Abstract: No abstract text available Text: Stratix GX FPGA Family Data Sheet February 2004, ver. 2.1 Introduction The Stratix GX family of devices is Altera's second FPGA family to combine high-speed serial transceivers with a scalable, high-performance logic array. Stratix GX devices include 4 to 20 high-speed transceiver	Original	PDF
EP1SGX25CF672C6N Abstract: EP1SGX40GF1020C6N EP1SGX25CF672C7 EP1SGX25CF672I6N Z0 607 MA GX 652 Text: Section I. Stratix GX Device Family Data Sheet This section provides the data sheet specifications for Stratix GX devices. It contains feature definitions of the internal architecture, configuration information, testing information, DC operating conditions,	Original	PDF	EP1SGX40GF1020C5 EP1SGX40G EP1SGX40GF1020C5N EP1SGX40GF1020C6 EP1SGX40GF1020C6N EP1SGX40GF1020C7 EP1SGX40GF1020C7N EP1SGX40GF1020I6 EP1SGX40GF1020I6N EP1SGX25CF672C6N EP1SGX25CF672C7 EP1SGX25CF672I6N Z0 607 MA GX 652
Untitled Abstract: No abstract text available Text: Section I. Stratix GX Device Family Data Sheet This section provides the data sheet specifications for Stratix GX devices. It contains feature definitions of the internal architecture, configuration information, testing information, DC operating conditions,	Original	PDF
pseudo-random noise generator Abstract: MAX4967 ENa 441 144bits Z0 607 MA GX 652 inter clock skew altera Text: Section I. Stratix GX Device Family Data Sheet This section provides the data sheet specifications for Stratix GX devices. It contains feature definitions of the internal architecture, configuration information, testing information, DC operating conditions,	Original	PDF
verilog code for 4 bit ripple COUNTER Abstract: Quartus II Handbook version 9.1 image processing Text: Section I. Stratix II GX Device Data Sheet This section provides designers with the data sheet specifications for Stratix II GX devices. They contain feature definitions of the transceivers, internal architecture, configuration and JTAG boundaryscan testing information, DC operating conditions, AC timing	Original	PDF
a 1757 transistor Abstract: Cyclone II FPGA vhdl code for asynchronous fifo TH 2028 3414 TRANSISTOR Text: Section I. Stratix II GX Device Data Sheet This section provides designers with the data sheet specifications for Stratix II GX devices. They contain feature definitions of the transceivers, internal architecture, configuration and JTAG boundaryscan testing information, DC operating conditions, AC timing	Original	PDF
transistor gx 734 Abstract: 1451 encoder bst 1046 Crossbar Switches SONET SDH vhdl code for 16 prbs generator din 2768 rx2 1107 MA1567 Text: Section I. Stratix II GX Device Data Sheet This section provides designers with the data sheet specifications for Stratix II GX devices. They contain feature definitions of the transceivers, internal architecture, configuration, and JTAG boundary-scan testing information, DC operating conditions, AC timing	Original	PDF
EP2SGX60EF1152C4N Abstract: equivalent transistor K 3562 EP2SGX60DF780I4N EP2SGX60EF1152C5 EP2SGX60DF780I4 EP2SGX60DF780C5 HD-SDI serializer EP2SGX60EF1152I4N EP2SGX130GF1508C5 Text: Section I. Stratix II GX Device Data Sheet This section provides designers with the data sheet specifications for Stratix II GX devices. They contain feature definitions of the transceivers, internal architecture, configuration, and JTAG boundary-scan testing information, DC operating conditions, AC timing	Original	PDF	EP2SGX130GF40C3ES EP2SGX130G EP2SGX130GF40C3NES EP2SGX130GF40C4ES EP2SGX130GF40C4NES EP2SGX130GF40C5ES EP2SGX130GF40C5NES EP2SGX130GF1508C3 EP2SGX130GF1508C3N EP2SGX130GF1508C4 EP2SGX60EF1152C4N equivalent transistor K 3562 EP2SGX60DF780I4N EP2SGX60EF1152C5 EP2SGX60DF780I4 EP2SGX60DF780C5 HD-SDI serializer EP2SGX60EF1152I4N EP2SGX130GF1508C5
HSTL standards Abstract: 15-V AGX52008-1 APEX20KC SSTL-18 Text: Section IV. I/O Standards This section provides information on Arria GX single-ended, voltage-referenced, and differential I/O standards. This section contains the following chapters: Revision History Altera Corporation • Chapter 8, Selectable I/O Standards in Arria GX Devices	Original	PDF
6A91 Abstract: No abstract text available Text: Section I. Stratix II GX Device Data Sheet This section provides designers with the data sheet specifications for Stratix II GX devices. They contain feature definitions of the transceivers, internal architecture, configuration and JTAG boundaryscan testing information, DC operating conditions, AC timing	Original	PDF	EP2SGX130 EP2SGX90 1152-pin 1508-pin 6A91
15-V Abstract: AGX52008-1 APEX20KC SSTL-18 Teradyne connector 72 pin Text: Section IV. I/O Standards This section provides information on Arria GX single-ended, voltage-referenced, and differential I/O standards. This section contains the following chapters: Revision History Altera Corporation • Chapter 8, Selectable I/O Standards in Arria GX Devices	Original	PDF
transistor gx 734 Abstract: HD-SDI serializer 16 bit parallel GX 6107 Text: Section I. Stratix II GX Device Data Sheet This section provides designers with the data sheet specifications for Stratix II GX devices. They contain feature definitions of the transceivers, internal architecture, configuration and JTAG boundaryscan testing information, DC operating conditions, AC timing	Original	PDF	EP2SGX130 EP2SGX90 1152-pin 1508-pin transistor gx 734 HD-SDI serializer 16 bit parallel GX 6107

Untitled Abstract: No abstract text available Text: Stratix GX November 2003, ver. 2.0 Introduction Preliminary Information Features. Altera Corporation DS-STXGX-2.0 L01-09828-00 FPGA Family Data Sheet The Stratix GX family of devices is Altera's® second FPGA family to combine high-speed serial transceivers with a scalable, high-performance	Original	PDF	L01-09828-00
Untitled Abstract: No abstract text available Text: Stratix GX November 2003, ver. 2.0 Introduction Preliminary Information Features. Altera Corporation DS-STXGX-2.0 FPGA Family Data Sheet The Stratix GX family of devices is Altera's® second FPGA family to combine high-speed serial transceivers with a scalable, high-performance	Original	PDF
oc-192 serdes Abstract: history of automatic phase selector TRANSISTOR D123 JC42 P802 SSTL-18 Compact PCI Backplane Block Diagram Altera source-synchronous Text: Section IV. I/O Standards This section provides information about the I/O standards and interfaces for Stratix and Stratix GX devices. This section includes the following chapters: Revision History • Chapter 16, Selectable I/O Standards in Stratix & Stratix GX Devices	Original	PDF	125-Gbps oc-192 serdes history of automatic phase selector TRANSISTOR D123 JC42 P802 SSTL-18 Compact PCI Backplane Block Diagram Altera source-synchronous
Untitled Abstract: No abstract text available Text: Section I. Stratix II GX Device Data Sheet This section provides designers with the data sheet specifications for Stratix II GX devices. They contain feature definitions of the transceivers, internal architecture, configuration and JTAG boundaryscan testing information, DC operating conditions, AC timing	Original	PDF
interfacing differential logic families 1998 Abstract: 15-V SSTL-18 HSTL standards Text: Section IV. I/O Standards This section provides information on Stratix II GX single-ended, voltage-referenced, and differential I/O standards. This section contains the following chapters: Revision History Altera Corporation • Chapter 10, Selectable I/O Standards in Stratix II & Stratix II GX	Original	PDF
MAX4967 Abstract: 10-Gigabit EP1SGX25CF672C7 Text: Stratix GX November 2003, ver. 2.0 Introduction Preliminary Information Features. Altera Corporation DS-STXGX-2.0 L01-09828-00 FPGA Family Data Sheet The Stratix GX family of devices is Altera's® second FPGA family to combine high-speed serial transceivers with a scalable, high-performance	Original	PDF	EP1SGX40DF1020C5 EP1SGX40D EP1SGX40DF1020C6 EP1SGX40DF1020C7 EP1SGX40GF1020C5 EP1SGX40G EP1SGX40GF1020C6 EP1SGX40GF1020C7 EP1SGX40* MAX4967 10-Gigabit EP1SGX25CF672C7
free verilog code of prbs pattern generator Abstract: No abstract text available Text: Section I. Stratix II GX Device Data Sheet This section provides designers with the data sheet specifications for Stratix II GX devices. They contain feature definitions of the transceivers, internal architecture, configuration, and JTAG boundary-scan testing information, DC operating conditions, AC timing	Original	PDF	EP2SGX130 EP2SGX90 1152-pin 1508-pin free verilog code of prbs pattern generator
verilog code of prbs pattern generator Abstract: transistor gx 734 EP2SGX130 Text: Section I. Stratix II GX Device Data Sheet This section provides designers with the data sheet specifications for Stratix II GX devices. They contain feature definitions of the transceivers, internal architecture, configuration, and JTAG boundary-scan testing information, DC operating conditions, AC timing	Original	PDF
8th class date sheet 2012 Abstract: date sheet 8th class 2012 2322 640 5 bst 1046 DN 2530 ITS DRIVER CIRCUIT vhdl code for pn sequence generator MA1567 Text: Section I. Stratix II GX Device Data Sheet This section provides designers with the data sheet specifications for Stratix II GX devices. They contain feature definitions of the transceivers, internal architecture, configuration, and JTAG boundary-scan testing information, DC operating conditions, AC timing	Original	PDF
AGX52009-1 Abstract: SSTL-18 XXXX7654 Text: 9. High-Speed Differential I/O Interfaces with DPA in Arria GX Devices AGX52009-1.01 Introduction The Arria GX device family offers up to 840-Mbps differential I/O capabilities to support source-synchronous communication protocols such as HyperTransport™ technology, Rapid I/O, XSBI, and SPI.	Original	PDF	AGX52009-1 840-Mbps SSTL-18 XXXX7654

GX 717 Search Results

GX 717 Price and Stock

Nexperia 74LV1T126GXH

Nexperia 74LV1T32GXH

Nexperia 74LV1T08GXH

Nexperia 74LVC1G14GX4-Q100Z

Nexperia 74AUP1G14GX4-Q100Z

GX 717 Datasheets Context Search

circuit diagram of inverting adder

EP1SGX25CF672C7

Untitled

EP1SGX25CF672C6N

Untitled

pseudo-random noise generator

verilog code for 4 bit ripple COUNTER

a 1757 transistor

transistor gx 734

EP2SGX60EF1152C4N

HSTL standards

6A91

15-V

transistor gx 734

Untitled

Untitled

oc-192 serdes

Untitled

interfacing differential logic families 1998

MAX4967

free verilog code of prbs pattern generator

verilog code of prbs pattern generator

8th class date sheet 2012

AGX52009-1