Please enter a valid full or partial manufacturer part number with a minimum of 3 letters or numbers

    FUNCTION OF X- OR GATES Search Results

    FUNCTION OF X- OR GATES Result Highlights (6)

    Part ECAD Model Manufacturer Description Download Buy
    TCTH022AE Toshiba Electronic Devices & Storage Corporation Over Temperature Detection IC / VDD=1.7~5.5V / IPTCO=10μA / IDD=11.3μA / Push-pull type / FLAG signal latch function Visit Toshiba Electronic Devices & Storage Corporation
    TCTH012BE Toshiba Electronic Devices & Storage Corporation Over Temperature Detection IC / VDD=1.7~5.5V / IPTCO=1μA / IDD=1.8μA / Open-drain type / FLAG signal latch function Visit Toshiba Electronic Devices & Storage Corporation
    TCTH012AE Toshiba Electronic Devices & Storage Corporation Over Temperature Detection IC / VDD=1.7~5.5V / IPTCO=1μA / IDD=1.8μA / Push-pull type / FLAG signal latch function Visit Toshiba Electronic Devices & Storage Corporation
    TCTH022BE Toshiba Electronic Devices & Storage Corporation Over Temperature Detection IC / VDD=1.7~5.5V / IPTCO=10μA / IDD=11.3μA / Open-drain type / FLAG signal latch function Visit Toshiba Electronic Devices & Storage Corporation
    TLP5702H Toshiba Electronic Devices & Storage Corporation Photocoupler (Gate Driver Coupler), High-Topr / IGBT driver, 5000 Vrms, SO6L Visit Toshiba Electronic Devices & Storage Corporation
    TLP5705H Toshiba Electronic Devices & Storage Corporation Photocoupler (Gate Driver Coupler), High-Topr / IGBT driver, 5000 Vrms, SO6L Visit Toshiba Electronic Devices & Storage Corporation

    FUNCTION OF X- OR GATES Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    Untitled

    Abstract: No abstract text available
    Text: MICROCIRCUIT DATA SHEET Original Creation Date: 06/25/97 Last Update Date: 07/08/97 Last Major Revision Date: 06/25/97 CN54F32-X REV 0A0 QUAD 2-INPUT OR GATE General Description This device contains four independent gates, each of which performs the logic OR function.


    Original     		PDF CN54F32-X 54F32 54F32DC CN74F CN54F M0001730

    Untitled

    Abstract: No abstract text available
    Text: Preliminary Revised October 2001 NC7SP57 • NC7SP58 TinyLogic ULP Universal Configurable 2-Input Logic Gates Preliminary General Description The NC7SP57 and the NC7SP58 are Universal Configurable 2-Input Logic Gates from Fairchild’s Ultra Low Power (ULP) Series of TinyLogic. Each device is capable


    Original     		PDF NC7SP57 NC7SP58 NC7SP57 NC7SP58

    Untitled

    Abstract: No abstract text available
    Text: Preliminary Revised October 2001 NC7SP57 • NC7SP58 TinyLogic Universal Configurable 2-Input Logic Gates Preliminary General Description The NC7SP57 and the NC7SP58 are Universal Configurable 2-Input Logic Gates from Fairchild’s Super Low Voltage Series of TinyLogic. Each device is capable of being


    Original     		PDF NC7SP57 NC7SP58 NC7SP57

    DIN405

    Abstract: elevator schematic PLS105 application of programmable array logic logic datasheet for elevator control circuit JKFF405 PLUS405-55
    Text: Philips Semiconductors Programmable Logic Devices Product specification Programmable logic sequencer 16 x 64 × 8 DESCRIPTION The PLUS405-55 device is a bipolar, programmable state machine of the Mealy type. Both the AND and the OR array are user-programmable. All 64 AND gates are


    Original     		PDF PLUS405-55 PLUS405-55 DIN405 NIN405 JKFF405 CK405 OUT405 DIN405 elevator schematic PLS105 application of programmable array logic logic datasheet for elevator control circuit JKFF405

    NC7SV57

    Abstract: No abstract text available
    Text: Revised September 2002 NC7SV57 • NC7SV58 TinyLogic ULP-A Universal Configurable 2-Input Logic Gates General Description Features The NC7SV57 and NC7SV58 are universal configurable 2-input logic gates from Fairchild’s Ultra Low Power ULP-A Series of TinyLogic. ULP-A is ideal for applications


    Original     		PDF NC7SV57 NC7SV58 NC7SV57

    smd transistor w19

    Abstract: Actel a42mx16 40MX 42MX A40MX02 A40MX04 A42MX09 A42MX16 A42MX24 A42MX36
    Text: 5.1 40MX and 42MX FPGA Families Fe a t ur es High C apaci t y • • • • • • Commercial, Military Temperature and MIL-STD-883 Ceramic Packages Single-Chip ASIC Alternative 3,000 to 54,000 System Gates Up to 2.5 kbits Configurable Dual-Port SRAM Fast Wide-Decode Circuitry


    Original     		PDF MIL-STD-883 35-Bit smd transistor w19 Actel a42mx16 40MX 42MX A40MX02 A40MX04 A42MX09 A42MX16 A42MX24 A42MX36

    A42MX16

    Abstract: 40MX 42MX A40MX02 A40MX04 A42MX09 A42MX24 A42MX36 32 bit ALU vhdl code 100PIN VQFP
    Text: v5.0 40MX and 42MX FPGA Families Fe a t ur es High C apaci t y • • • • • • Commercial, Military Temperature and MIL-STD-883 Ceramic Packages Single-Chip ASIC Alternative 3,000 to 54,000 System Gates Up to 2.5 kbits Configurable Dual-Port SRAM Fast Wide-Decode Circuitry


    Original     		PDF MIL-STD-883 35-Bit A42MX16 40MX 42MX A40MX02 A40MX04 A42MX09 A42MX24 A42MX36 32 bit ALU vhdl code 100PIN VQFP

    pin configuration of logic gates

    Abstract: NC7SV57 NC7SV57FHX NC7SV57L6X NC7SV57P6X NC7SV58 NC7SV58FHX NC7SV58L6X NC7SV58P6X logic gates pin configuration
    Text: NC7SV57 / NC7SV58 TinyLogic ULP-A Universal Configurable Two-Input Logic Gates Features Description ƒ ƒ 0.9V to 3.6V VCC Supply Operation ƒ Extremely High Speed tPD - 2.5ns: Typical for 2.7V to 3.6V VCC - 3.1ns: Typical for 2.3V to 2.7V VCC - 4.0ns: Typical for 1.65V to 1.95V VCC


    Original     		PDF NC7SV57 NC7SV58 NC7SV58 NC7SV57 NC7V58 pin configuration of logic gates NC7SV57FHX NC7SV57L6X NC7SV57P6X NC7SV58FHX NC7SV58L6X NC7SV58P6X logic gates pin configuration

    antifuse programming technology

    Abstract: 40MX 42MX A40MX02 A40MX04 A42MX09 A42MX16 A42MX24 A42MX36 42MX24
    Text: v6.0 40MX and 42MX FPGA Families Fe a t ur es High C apaci t y • • • • • • Commercial, Military Temperature, and MIL-STD-883 Ceramic Packages Single-Chip ASIC Alternative 3,000 to 54,000 System Gates Up to 2.5 kbits Configurable Dual-Port SRAM


    Original     		PDF MIL-STD-883 35-Bit antifuse programming technology 40MX 42MX A40MX02 A40MX04 A42MX09 A42MX16 A42MX24 A42MX36 42MX24

    DM74ALS27

    Abstract: No abstract text available
    Text: DM74ALS27 Triple 3-Input NOR Gate tm Features General Description • Switching specifications at 50pF This device contains three independent gates, each of which performs the logic NOR function. ■ Switching specifications guaranteed over full temperature and VCC range


    Original     		PDF DM74ALS27 DM74ALS27M 14-Lead MS-012,

    NC7SP57

    Abstract: NC7SP57L6X NC7SP57P6X NC7SP58 NC7SP58L6X NC7SP58P6X
    Text: Revised June 2002 NC7SP57 • NC7SP58 TinyLogic ULP Universal Configurable 2-Input Logic Gates General Description Features The NC7SP57 and the NC7SP58 are Universal Configurable 2-Input Logic Gates from Fairchild’s Ultra Low Power ULP Series of TinyLogic. Ideal for applications


    Original     		PDF NC7SP57 NC7SP58 NC7SP57 NC7SP58 NC7SP57L6X NC7SP57P6X NC7SP58L6X NC7SP58P6X

    GD74F08

    Abstract: No abstract text available
    Text: PRELIMINARY DATA SHEET GD74F08 QUAD 2-INPUT AND GATE Description This device contains four independent 2input AND gates, each of which performs the Boolean functions Y = A»B or Y = A+B. Function Table each gate Inputs Outputs A B Y H H H L X L X L L X Im m a te r ia l


    OCR Scan     		PDF GD74F08 -18mA GD74F08

    Untitled

    Abstract: No abstract text available
    Text: National Semiconductor MICROCIRCUIT DATA SHEET Original Creation Date: 12/06/96 Last Update D a t e : 06/19/97 Last Major Revision D a t e : 12/06/96 CN74F32-X REV OBO QUAD 2-INPUT OR GATE General Description This device contains four independent gates, each of which performs the logic OR function.


    OCR Scan     		PDF CN74F32-X 74F32 74F32DC M0001330

    HG62F

    Abstract: V/HG62F HG62F43
    Text: #U 210 HG62F SERIES Hitachi CMOS Gate Array High I/O to Gate Ratio JANUARY, 1990 0 H IT A C H I The F series consists of 6 masterslices ranging from 2,178 to 10,076 available gates with high I/O pin counts ranging from 136 pins to 208 pins. The HG62F series is a mastersliced gate array fabricated on 1.0


    OCR Scan     		PDF HG62F V/HG62F HG62F43

    AM2019

    Abstract: 2-bit half adder layout AX253 AX201 AM2001 AX261
    Text: * Am3525 Mask-Programmable Gate Array With ECL RAM PRELIMINARY > 3 DISTINCTIVE CHARACTERISTICS • • • Up to 3718 equivalent gates - 416 internal cells - Up to 135 l/O s 1152 bits of ECL RAM 1K with byte-wide parity - Worst case T a a (access time) = 5.5 ns


    OCR Scan     		PDF Am3525 TC002800 7321A 7322A AM2019 2-bit half adder layout AX253 AX201 AM2001 AX261

    AOX2053

    Abstract: No abstract text available
    Text: ADVANC ED MICRO DEVICES 7b D E j 05575.25 0020=177 3 g " 025 7525 ADVANCED MICRO DEVICES r- Am3550 76C 2 0977 T - 4 2 - 1 1 —1 5 Mixed ECL/TTL I/O Mask-Programmable Gate Array PRELIMINARY DISTINCTIVE CHARACTERISTICS Up to 6228 equivalent gates - 576 internal cells


    OCR Scan     		PDF Am3550 WFR02682 AOX2053

    Untitled

    Abstract: No abstract text available
    Text: Philips Semiconductors Product specification Programmable logic sequencers 16 x 64 x 8 PLUS405-37/-45 DESCRIPTION • T TL com patible The PLUS405 devices are bipolar, program m able state machines of the M ealy type. Both the AND and the OR array are user-program m able. All 64 AND gates are connected to the 16


    OCR Scan     		PDF PLUS405-37/-45 PLUS405 MO-047AB OT261-3

    am2022

    Abstract: am22 full adder circuit using xor and nand gates AM2031 AM2024 AM2051 t950 half adder circuit using nor and nand gates ax253 AM290
    Text: Am 3525 Mask-Programmable Gate Array With ECL RAM PRELIMINARY > 3 DISTINCTIVE CHARACTERISTICS Up to 3718 equivalent gates - 416 internal cells - Up to 135 l/O s 1152 bits of ECL RAM 1K with byte-wide parity - Worst case T a a (access time) = 5.5 ns High-performance, low-power ECL gates


    OCR Scan     		PDF Am3525 Am3525 TC002800 WF010980 7321A D7322A am2022 am22 full adder circuit using xor and nand gates AM2031 AM2024 AM2051 t950 half adder circuit using nor and nand gates ax253 AM290

    XC95288

    Abstract: No abstract text available
    Text: flXIU N X XC95286 In-System Programmable CPLD October 28, 1997 Version 2.0 Preliminary Product Specification Features MC h p (1.7) + MC lp (0.9) + MC (0.006 m A/M Hz) f • 15 ns pin-to-pin logic delays on all pins Where: • • • • fcNT to MHz 288 macrocells with 6,400 usable gates


    OCR Scan     		PDF XC95286 36V18 boundary-scaE15, XC95288 HQ208 208-Pin BG352 352-Pin XC95288

    Untitled

    Abstract: No abstract text available
    Text: flX IU N X XC9536 In-System Programmable CPLD November 10, 1997 Version 2.0 Product Specification Features Power Management • 5 ns pin-to-pin logic delays on all pins • • • • fcNT to MHz 36 macrocells with 800 usable gates Up to 34 user I/O pins


    OCR Scan     		PDF XC9536 36V18 44-Pin XC9536

    Untitled

    Abstract: No abstract text available
    Text: flX IU N X XC9536 In-System Programmable CPLD October 29, 1997 Version 2.0 Product Specification Features Power Management 5 ns pin-to-pin logic delays on all pins • • • • • • • • • • • • • fcNT to MHz 36 macrocells with 800 usable gates


    OCR Scan     		PDF XC9536 36V18 44-Pin XC9536

    AM3526

    Abstract: 2-bit half adder AM312 AM290 AM2019 AM2001 002074
    Text: ADVANCED MICRO D E V I C E S 7b D E j 0ES7SHS OOSOTbM ADVANCED MICRO D E V ICES 5 | 76C ¿ 0 9 6 4 D “¿T -.4-2-11-13 I" Mask-Programmable Gate Array With ECL RAM PRELIMINARY DISTINCTIVE CHARACTERISTICS Up to 3718 equivalent gates - 416 Internal cells - Up to 135 l/O s


    OCR Scan     		PDF 1T-42-11-13 WF001164 00ECH7Ã T-42-11-13 AM3526 2-bit half adder AM312 AM290 AM2019 AM2001 002074

    siemens master drive circuit diagram

    Abstract: SR flip flop IC toshiba tc110g TC110G jk flip flop to d flip flop conversion SC11C1 JK flip flop IC siemens Nand gate scxc1 SR flip flop IC pin diagram
    Text: SIEM EN S ASIC Product Description SCxC1 Family CMOS Gate Arrays FEATURES • Alternate source of Toshiba TC110G family ■ Densities up to 129,000 raw gates ■ Channelless “ sea of gates” architecture ■ 1.5 firn drawn CMOS technology, scalable to 1.0 /¿m


    OCR Scan     		PDF TC110G M33S004 siemens master drive circuit diagram SR flip flop IC toshiba tc110g jk flip flop to d flip flop conversion SC11C1 JK flip flop IC siemens Nand gate scxc1 SR flip flop IC pin diagram

    FC SUFFIX altera

    Abstract: No abstract text available
    Text: Classic EPLD Family Data Sheet M arch 1995, ver. 2 Features • ■ ■ ■ ■ ■ ■ ■ ■ ■ Table 1. Classic Device Features Feature EP22V10 EP22V10E EPB10 EP610T EP610I EP910 EP910T EP910I EP1810 EP1810T Available gates 400 600 600 900 900 1,800 Usable gates


    OCR Scan     		PDF