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    FUNCTION OF X- OR GATES Search Results

    FUNCTION OF X- OR GATES Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    SN54F64J/B Rochester Electronics LLC 54F64 - AND-OR-Invert Function Visit Rochester Electronics LLC Buy
    TCTH022AE Toshiba Electronic Devices & Storage Corporation Over Temperature Detection IC / VDD=1.7~5.5V / IPTCO=10μA / IDD=11.3μA / Push-pull type / FLAG signal latch function Visit Toshiba Electronic Devices & Storage Corporation
    TCTH012BE Toshiba Electronic Devices & Storage Corporation Over Temperature Detection IC / VDD=1.7~5.5V / IPTCO=1μA / IDD=1.8μA / Open-drain type / FLAG signal latch function Visit Toshiba Electronic Devices & Storage Corporation
    TCTH012AE Toshiba Electronic Devices & Storage Corporation Over Temperature Detection IC / VDD=1.7~5.5V / IPTCO=1μA / IDD=1.8μA / Push-pull type / FLAG signal latch function Visit Toshiba Electronic Devices & Storage Corporation
    TCTH022BE Toshiba Electronic Devices & Storage Corporation Over Temperature Detection IC / VDD=1.7~5.5V / IPTCO=10μA / IDD=11.3μA / Open-drain type / FLAG signal latch function Visit Toshiba Electronic Devices & Storage Corporation

    FUNCTION OF X- OR GATES Datasheets Context Search

    Catalog Datasheet MFG & Type Document Tags PDF

    54LS32

    Abstract: L032
    Text: MICROCIRCUIT DATA SHEET Original Creation Date: 04/22/98 Last Update Date: 06/16/98 Last Major Revision Date: 04/22/98 MNDM54LS32-X REV 1A0 QUAD 2-INPUT OR GATE General Description This device contains four independent gates, each of which perform the logic OR function.


    Original     		MNDM54LS32-X 54LS32 DM54LS32E/883 DM54LS32J/883 DM54LS32W/883 MIL-STD-883, M0001245 54LS32 L032 PDF

    Untitled

    Abstract: No abstract text available
    Text: MICROCIRCUIT DATA SHEET Original Creation Date: 06/25/97 Last Update Date: 07/08/97 Last Major Revision Date: 06/25/97 CN54F32-X REV 0A0 QUAD 2-INPUT OR GATE General Description This device contains four independent gates, each of which performs the logic OR function.


    Original     		CN54F32-X 54F32 54F32DC CN74F CN54F M0001730 PDF

    54F32LMQB

    Abstract: 54F32 54F32DMQB 54F32FMQB MN54F32-X
    Text: MILITARY DATA SHEET Original Creation Date: 03/12/96 Last Update Date: 07/30/96 Last Major Revision Date: 03/12/96 MN54F32-X REV 1A0 QUAD 2-INPUT OR GATE General Description This device contains four independent gates, each of which performs the logic OR function.


    Original     		MN54F32-X 54F32 54F32DMQB 54F32FMQB 54F32LMQB MIL-STD-883, -55/125C 54F32LMQB 54F32 54F32DMQB 54F32FMQB PDF

    schmitt trigger 4093

    Abstract: D16841 4017 decade counter 1-of-10 dual differential line driver 88c30 HC 4093 4013 astable 16-LINE TO 4-LINE PRIORITY ENCODERS 7 segment 40192 88c29 4011 astable
    Text: Revised April 1999 Functional Selection Table 1999 Fairchild Semiconductor Corporation MS500117.prf www.fairchildsemi.com Functional Selection Table February 1998 Gates Function CROSSVOLT Device Leads FACT FAST FASTr ALS AS LS S TTL ABT VCX LCX LVX LVT LVQ AC ACT


    Original     		MS500117 schmitt trigger 4093 D16841 4017 decade counter 1-of-10 dual differential line driver 88c30 HC 4093 4013 astable 16-LINE TO 4-LINE PRIORITY ENCODERS 7 segment 40192 88c29 4011 astable PDF

    MIL-STD-806

    Abstract: 5 inputs OR gate truth table 4 inputs OR gate truth table 6 inputs OR gate truth table truth table for 7 inputs OR gate SCHMITT INVERTER 6 inputs NOR gate truth table M1C21 demultiplexer truth table truth table for 4 inputs OR gate
    Text: [4] Logic Symbols and Truth Tables [ 4 ] Logic Symbols and Truth Table 1. How to Read MIL-Type Logic Symbols Table 1.1 shows the MIL-type logic symbols used for high-speed CMOS ICs. This logic chart is based on MIL-STD-806. The clocked inverter and transmission gates have specific symbols.


    Original     		MIL-STD-806. MIL-STD-806 5 inputs OR gate truth table 4 inputs OR gate truth table 6 inputs OR gate truth table truth table for 7 inputs OR gate SCHMITT INVERTER 6 inputs NOR gate truth table M1C21 demultiplexer truth table truth table for 4 inputs OR gate PDF

    NC7SP57

    Abstract: NC7SP57L6X NC7SP57P6X NC7SP58 NC7SP58L6X NC7SP58P6X
    Text: Preliminary Revised November 2001 NC7SP57 • NC7SP58 TinyLogic ULP Universal Configurable 2-Input Logic Gates Preliminary General Description The NC7SP57 and the NC7SP58 are Universal Configurable 2-Input Logic Gates from Fairchild’s Ultra Low Power (ULP) Series of TinyLogic. Each device is capable


    Original     		NC7SP57 NC7SP58 NC7SP57 NC7SP58 NC7SP57L6X NC7SP57P6X NC7SP58L6X NC7SP58P6X PDF

    digital clock using logic gates

    Abstract: specifications of and logic gates digital clock using gates LCA300K datasheets of the basic logic gates or gates 8 bit XOR Gates 20K Preset datasheet driving gates EP20K100E
    Text: Gate Counting Methodology for APEX 20K Devices September 1999, ver. 1.01 Introduction Application Note 110 Altera’s APEXTM 20K device family offers an innovative combination of look-up table LUT logic, product-term logic, and embedded memory. Ranging from 162,000 to 2,500,000 maximum system gates, the


    Original     		PDF

    Untitled

    Abstract: No abstract text available
    Text: Preliminary Revised October 2001 NC7SP57 • NC7SP58 TinyLogic ULP Universal Configurable 2-Input Logic Gates Preliminary General Description The NC7SP57 and the NC7SP58 are Universal Configurable 2-Input Logic Gates from Fairchild’s Ultra Low Power (ULP) Series of TinyLogic. Each device is capable


    Original     		NC7SP57 NC7SP58 NC7SP57 NC7SP58 PDF

    Untitled

    Abstract: No abstract text available
    Text: Preliminary Revised October 2001 NC7SP57 • NC7SP58 TinyLogic Universal Configurable 2-Input Logic Gates Preliminary General Description The NC7SP57 and the NC7SP58 are Universal Configurable 2-Input Logic Gates from Fairchild’s Super Low Voltage Series of TinyLogic. Each device is capable of being


    Original     		NC7SP57 NC7SP58 NC7SP57 PDF

    NXP 74LVC1G

    Abstract: SN74LVC2G TC7SZU04 "cross-reference" 74AHC1G14 SOT-23 SCYT129E SN74AUP AUP1G00 74AUP3G17 TC7SG125 nxp Cross-reference
    Text: Little Logic Guide Gates Configurables Signal Switches Translators www.ti.com/littlelogic 2012 Little Logic Guide ➔ Table of Contents Overview 3 Little Logic Products by Performance 4 Logic Migration to 1.8-V Future . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4


    Original     		PDF

    THERMAL Fuse m20 tf 115 c

    Abstract: SX v3.1 REQ64 A54SX08 A54SX16 A54SX32 PAR64 313 pin PBGA fq1200 THERMAL Fuse l20 tf 115 c
    Text: v3.2 SX Family FPGAs u e Leading Edge Performance • • • • Features 320 MHz Internal Performance 3.7 ns Clock-to-Out Pin-to-Pin 0.1 ns Input Setup 0.25 ns Clock Skew • • • • • • • • Specifications • • • • 12,000 to 48,000 System Gates


    Original     		PDF

    Untitled

    Abstract: No abstract text available
    Text: v3.2 SX Family FPGAs u e Leading Edge Performance • • • • Features 320 MHz Internal Performance 3.7 ns Clock-to-Out Pin-to-Pin 0.1 ns Input Setup 0.25 ns Clock Skew • • • • • • • • Specifications • • • • 12,000 to 48,000 System Gates


    Original     		PDF

    82S153

    Abstract: PLS153 24 SIGNETICS 82S153A/BRA Programmable Logic Array 2 input ex-or gate 14 pin ic 82S153A PLS153A fusible chip resistor pls153a jedec
    Text: Product specification S ign etics Program m able L o gic Prod ucts Field programmable logic array 18 x 42 x 10 DESCRIPTION LOGIC FUNCTION • 10 OR gates The 82S153A is a two-tevel logic element, consisting of 42 AND gates and 10 OR gates with fusible link connections for programming


    OCR Scan     		82S153A PLS153A) 82S153A 22-Lead T-90-20 14-Pin 16-Pln 82S153 PLS153 24 SIGNETICS 82S153A/BRA Programmable Logic Array 2 input ex-or gate 14 pin ic PLS153A fusible chip resistor pls153a jedec PDF

    Untitled

    Abstract: No abstract text available
    Text: § 5 2 National Semiconductor DM74S51 Dual 2-Wide 2-Input AND-OR-INVERT Gates General Description This device contains two independent combinations of gates each of which performs the logic AND-OR-INVERT function. Connection Diagram Dual-In-Line Package WA KE NO E X T E R N A L


    OCR Scan     		DM74S51 DM74S51N DM74S PDF

    GD74F08

    Abstract: No abstract text available
    Text: PRELIMINARY DATA SHEET GD74F08 QUAD 2-INPUT AND GATE Description This device contains four independent 2input AND gates, each of which performs the Boolean functions Y = A»B or Y = A+B. Function Table each gate Inputs Outputs A B Y H H H L X L X L L X Im m a te r ia l


    OCR Scan     		GD74F08 -18mA GD74F08 PDF

    Untitled

    Abstract: No abstract text available
    Text: National Semiconductor MICROCIRCUIT DATA SHEET Original Creation Date: 12/06/96 Last Update D a t e : 06/19/97 Last Major Revision D a t e : 12/06/96 CN74F32-X REV OBO QUAD 2-INPUT OR GATE General Description This device contains four independent gates, each of which performs the logic OR function.


    OCR Scan     		CN74F32-X 74F32 74F32DC M0001330 PDF

    xor IC

    Abstract: MOTOROLA ECL IC of XNOR GATE
    Text: 'O' SY N E R G Y QUINT 2-INPUT 3Y10E1Û7 < O R / X N O R GA T E Y 10 R E i 0 7 S E M IC O N D U C T O R D E S C R IP TIO N FEATURES • ■ ■ ■ ■ 600ps max. propagation delay Extended 100E Vee range of -4.2V to -5.5V True and complementary outputs OR/NOR function outputs


    OCR Scan     		3Y10E1 600ps SV10/100E107 MC10E/100E107 Typ410 SY10E107JC SY10E107JCTR SY100E107JC SY100E107JCTR J28-1 xor IC MOTOROLA ECL IC of XNOR GATE PDF

    Philips Semiconductors Selection Guide

    Abstract: 74ALS08
    Text: Philips Semiconductors Functional selection guide GATES FUNCTION INVERTERS NAND NOR DEVICE NUMBER NUMBER OF PINS Hex inverters 74ALS04B 14 Quad 2-input 74ALS00A 14 Triple 3-input 74ALS10A 14 Dual 4-input 74ALS20A 14 8-input 74ALS30A 14 Quint 2-input NAND, open collector


    OCR Scan     		74ALS04B 74ALS00A 74ALS10A 74ALS20A 74ALS30A 74ALS38A 74ALS02 74ALS27 74ALS08 74ALS11A Philips Semiconductors Selection Guide PDF

    DM74AS881BNT

    Abstract: No abstract text available
    Text: 881B O T National Semiconductor DM74AS881B 4-Bit Arithmetic Logic Unit/Function Generator General Description Features The DM74AS881B is an arithmetic logic unit ALU /function generator that has a complexity of 77 equivalent gates, re­ spectively, on a monolithic chip. These circuits perform 16


    OCR Scan     		DM74AS881B DM74AS881BNT PDF

    Untitled

    Abstract: No abstract text available
    Text: NATIONAL SEMICOND -CLOGIO 31E D WSQliaa OüblblQ 7 T - h Q - u - o o DM74AS881B 4-Bit Arithmetic Logic Unit/Function Generator General Description Features The DM74AS881B is an arithmetic logic unit ALU /function generator that has a complexity of 77 equivalent gates, re­


    OCR Scan     		DM74AS881B PDF

    HG62S026

    Abstract: No abstract text available
    Text: HG62S Series High-Speed CMOS Gate Array H IT A C H I* Features Description The HG62S series free-channel gate arrays utilize a 0.8-/un CMOS process with triple metal intercon­ nect technology. The series consists of 6 master slices ranging from 26,054 to 250,000 raw gates.


    OCR Scan     		HG62S HG62E/F HG62S, PC-400 HG62S026 PDF

    HG62F

    Abstract: V/HG62F HG62F43
    Text: #U 210 HG62F SERIES Hitachi CMOS Gate Array High I/O to Gate Ratio JANUARY, 1990 0 H IT A C H I The F series consists of 6 masterslices ranging from 2,178 to 10,076 available gates with high I/O pin counts ranging from 136 pins to 208 pins. The HG62F series is a mastersliced gate array fabricated on 1.0


    OCR Scan     		HG62F V/HG62F HG62F43 PDF

    Untitled

    Abstract: No abstract text available
    Text: Advance Data Sheet February 1993 £ = — AT&T Microelectronics Optimized Reconfigurable Cell Array ORCA Series Field-Programmable Gate Arrays Features • High density: 3500 to 22,000 usable gates ■ High I/O: up to 288 usable I/O ■ High performance: 80 MHz system clock rate


    OCR Scan     		16-bit DS92-099FPGA PDF

    AM2019

    Abstract: 2-bit half adder layout AX253 AX201 AM2001 AX261
    Text: * Am3525 Mask-Programmable Gate Array With ECL RAM PRELIMINARY > 3 DISTINCTIVE CHARACTERISTICS • • • Up to 3718 equivalent gates - 416 internal cells - Up to 135 l/O s 1152 bits of ECL RAM 1K with byte-wide parity - Worst case T a a (access time) = 5.5 ns


    OCR Scan     		Am3525 TC002800 7321A 7322A AM2019 2-bit half adder layout AX253 AX201 AM2001 AX261 PDF