FPLA APPLICATIONS Search Results

FPLA APPLICATIONS Result Highlights (5)

Part	Manufacturer	Description
CA3079	Rochester Electronics LLC	CA3079 - Zero-Voltage Switches for 50-60Hz and 400Hz Thyristor Control Applications
CA3059	Rochester Electronics LLC	CA3059 - Zero-Voltage Switches for 50-60Hz and 400Hz Thyristor Control Applications
CA3059-G	Rochester Electronics LLC	CA3059 - Zero-Voltage Switches for 50-60Hz and 400Hz Thyristor Control Applications
TCM3105NL	Rochester Electronics LLC	TCM3105NL - FSK Modem, PDIP16
AM79865JC	Rochester Electronics LLC	AM79865 -Physical Data Transmitter

FPLA APPLICATIONS Datasheets Context Search

Catalog Datasheet	Type	Document Tags	PDF
22V10 Abstract: No abstract text available Text: CHAPTER 2 M A P L 2 44 /2 68 ADVANCE INFO RM ATIO N 2.1 Introduction The MAPL244 and MAPL268 both integrate FPLA and PAL architec tures, which make it suitable for large sequential and combinato rial applications. The FPLA is similar to the MAPL28, thus allowing	OCR Scan	MAPL244/268 MAPL244 MAPL268 MAPL28, 22V10, TSP-MAPL-01 TSP-MAPL-02 22V10	PDF
Untitled Abstract: No abstract text available Text: INTERNATIONAL CMOS TECHNOLOGY, INC. PEEL253 CMOS Programmable Electrically Erasable Logic Device Features • ADVANCED CMOS EEPROM TECHNOLOGY ■ FPLA ARCHITECTURE ■ COMPATIBLE PERFORMANCE — tpD = 30ns max, to E = 30ns max SUPERSET REPLACEMENT FOR PLS153	OCR Scan	PEEL253 PLS153 terms/10	PDF
PEEL programming Abstract: PEEL173 Erasable Programmable Logic Device 610 PLS173 8-12pF Text: AMI PEEL 173 SEMICONDUCTORS CMOS Programmable Electrically Erasable Logic Device February 1993 Features General Description FPLA Architecture The AMI PEEL173 is a CMOS Programmable Electrically Erasable Logic device that provides a high-performance, low-power,	OCR Scan	PLS173 PEEL173 PEEL programming Erasable Programmable Logic Device 610 PLS173 8-12pF	PDF
1B60 Abstract: PEEL programming msi ms 1772 Text: AMI PEEL 173 SEMICONDUCTORS CM O S Programmable Electrically Erasable Logic Device February 1993 Features General Description FPLA Architecture The AMI PEEL173 is a CMOS Programmable Electrically Erasable Logic device that provides a high-performance, low-power,	OCR Scan	PEEL173 1B60 PEEL programming msi ms 1772	PDF
AL6002 Abstract: ic 8155 block diagram RT 8204 Text: GAL6002 Lattice High Performance E2CMOS FPLA Generic Array Logic Semiconductor Corporation FUNCTIONAL BLOCK DIAGRAM FEATURES • HIGH PERFORMANCE E2CMOS TECHNOLOGY — 15ns Maximum Propagation Delay — 75MHz Maximum Frequency — 6.5ns Maximum Clock to Output Delay	OCR Scan	75MHz Tested/100% 100ms) GAL6002 AL6002 ic 8155 block diagram RT 8204	PDF
AL6002 Abstract: lt 8232 ic 8155 block diagram lt 8219 pin diagram of 8203 LT 8216 al600 lt 8227 LT 8233 lt 8239 Text: GAL6002 Lattica High Performance E2CMOS FPLA Generic Array Logic Semiconductor Corporation FEATURES FUNCTIONAL BLOCK DIAGRAM • HIGH PERFORMANCE E2CMOS TECHNOLOGY — 15ns Maximum Propagation Delay — 75MHz Maximum Frequency — 6.5ns Maximum Clock to Output Delay	OCR Scan	75MHz Tested/100% 100ms) GAL6002 AL6002 lt 8232 ic 8155 block diagram lt 8219 pin diagram of 8203 LT 8216 al600 lt 8227 LT 8233 lt 8239	PDF
lt 8224 Abstract: lt 8232 lt 8227 lt 8239 LT 8195 lt 8225 LT 8216 fn521 lt 8220 ep 8212 Text: Specifications GAL6002 GAL6002 High Performance E2CMOS FPLA Generic Array Logic FEATURES FUNCTIONAL BLOCK DIAGRAM • HIGH PERFORMANCE E CMOS TECHNOLOGY — 15ns Maximum Propagation Delay — 75MHz Maximum Frequency — 6.5ns Maximum Clock to Output Delay	Original	GAL6002 75MHz 100ms) lt 8224 lt 8232 lt 8227 lt 8239 LT 8195 lt 8225 LT 8216 fn521 lt 8220 ep 8212	PDF
lt 8232 Abstract: LT 8233 lt 8217 LT 8209 LT 8223 lt 8219 GAL6002 GAL6002B-15LJ GAL6002B-15LP R/diode lt 8232 Text: Specifications GAL6002 GAL6002 High Performance E2CMOS FPLA Generic Array Logic FUNCTIONAL BLOCK DIAGRAM FEATURES • HIGH PERFORMANCE E CMOS TECHNOLOGY — 15ns Maximum Propagation Delay — 75MHz Maximum Frequency — 6.5ns Maximum Clock to Output Delay	Original	GAL6002 75MHz Tested/100% 100ms) lt 8232 LT 8233 lt 8217 LT 8209 LT 8223 lt 8219 GAL6002 GAL6002B-15LJ GAL6002B-15LP R/diode lt 8232	PDF
GAL6001 Abstract: GAL6001B-30LJ GAL6001B-30LP 8178 Text: Specifications GAL6001 GAL6001 High Performance E2CMOS FPLA Generic Array Logic FEATURES FUNCTIONAL BLOCK DIAGRAM ICLK • HIGH PERFORMANCE E2CMOS TECHNOLOGY — 30ns Maximum Propagation Delay — 27MHz Maximum Frequency — 12ns Maximum Clock to Output Delay	Original	GAL6001 27MHz Tested/100% 100ms) GAL6001 GAL6001B-30LJ GAL6001B-30LP 8178	PDF
GAL6001 Abstract: GAL6001B-30LJ GAL6001B-30LP Text: Specifications GAL6001 GAL6001 High Performance E2CMOS FPLA Generic Array Logic FEATURES FUNCTIONAL BLOCK DIAGRAM ICLK • HIGH PERFORMANCE E2CMOS TECHNOLOGY — 30ns Maximum Propagation Delay — 27MHz Maximum Frequency — 12ns Maximum Clock to Output Delay	Original	GAL6001 27MHz Tested/100% 100ms) GAL6001 GAL6001B-30LJ GAL6001B-30LP	PDF
273-12/PEELT273-15 Abstract: PEEL22CV10ZP-25 Text: Preliminary Information INC. PEEL 273-12/PEELT273-15 CMOS Programmable Electrically Erasable Logic Device Features • ADVANCED CM OS EEPROM TECHNOLOGY ■ FPLA ARCHITECTURE ■ LOW POW ER CONSUMPTION ■ SUPERSET REPLACEM ENT FOR PLS173 — — — —	OCR Scan	273-12/PEELT273-15 PLS173 PEEL18CV8P-25 228KO PEEL18CV8P-10/15 PEEL20CG1 OP-25 PEEL20CG1OAP-10/15 273-12/PEELT273-15 PEEL22CV10ZP-25	PDF
Untitled Abstract: No abstract text available Text: Lattice GAL6001B High Performance E2CMOS FPLA Generic Array Logic •■■■ FEATURES FUNCTIONAL BLOCK DIAGRAM • HIGH PERFORMANCE E’CMOS* TECHNOLOGY — 30ns Maximum Propagation Delay — 27MHz Maximum Frequency — 12ns Max. Clock to Output Delay	OCR Scan	GAL6001B 27MHz 100ms)	PDF
ta 8221 H Abstract: GAL6001 e2cmos technology GAL6001B-30LJ GAL6001B-30LP Text: GAL6001 High Performance E2CMOS FPLA Generic Array Logic Features Functional Block Diagram • HIGH PERFORMANCE E2CMOS TECHNOLOGY — 30ns Maximum Propagation Delay — 27MHz Maximum Frequency — 12ns Maximum Clock to Output Delay — TTL Compatible 16mA Outputs	Original	GAL6001 27MHz Tested/100% 100ms) ta 8221 H GAL6001 e2cmos technology GAL6001B-30LJ GAL6001B-30LP	PDF
lt 8232 Abstract: LT 8216 LT 8215 LT 8209 lt 8227 lt 8221 lt 8225 lt 8239 lt 8219 lt 8224 Text: Specifications GAL6002 GAL6002 High Performance E2CMOS FPLA Generic Array Logic FUNCTIONAL BLOCK DIAGRAM FEATURES • HIGH PERFORMANCE E CMOS TECHNOLOGY — 15ns Maximum Propagation Delay — 75MHz Maximum Frequency — 6.5ns Maximum Clock to Output Delay	Original	GAL6002 75MHz Tested/100% 100ms) lt 8232 LT 8216 LT 8215 LT 8209 lt 8227 lt 8221 lt 8225 lt 8239 lt 8219 lt 8224	PDF

signetics 82s100 Abstract: 82S100-I fpla 82S100 82S101 825100 82S100 programming 82S100/BXA Text: s ig n o tic s BIPOLAR FIELD-PROGRAMMABLE LOGIC ARRAY 16X8X48 FPLA 82S101 (OPEN COLLECTOR) _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 82S100 (TRI-STATE) O B JEC T IV E SPECIFICATION A P R IL 1975 825100 825101 DIGITAL 8000 SERIES TTL/MEMORY DESCRIPTION PIN CONFIGURATION	OCR Scan	16X8X48 82S101 82S100 16-input signetics 82s100 82S100-I fpla 82S100 82S101 825100 82S100 programming 82S100/BXA	PDF
GAL6001-30P Abstract: ic 8155 block diagram GAL6001-30J Text: Lattice GAL6002B High Performance E2CMOS FPLA Generic Array Logic FUNCTIONAL BLOCK DIAGRAM FEATURES • HIGH PERFORMANCE ECMOS TECHNOLOGY — 15ns Maximum Propagation Delay — 75MHz Maximum Frequency — 6.5ns Max. Clock to Output Delay — TTL Compatible 16mA Outputs	OCR Scan	GAL6002B 75MHz 100ms) GAL6001-30P ic 8155 block diagram GAL6001-30J	PDF
LT 8232 Abstract: LT 8215 lt 8225 LT 8224 lt 8220 lt 8228 lt 8239 LT 8229 LT 8233 lt 8227 Text: GAL6002 High Performance E2CMOS FPLA Generic Array Logic Features Functional Block Diagram ICLK • HIGH PERFORMANCE E2CMOS TECHNOLOGY — 15ns Maximum Propagation Delay — 75MHz Maximum Frequency — 6.5ns Maximum Clock to Output Delay — TTL Compatible 16mA Outputs	Original	GAL6002 75MHz Tested/100% 100ms) LT 8232 LT 8215 lt 8225 LT 8224 lt 8220 lt 8228 lt 8239 LT 8229 LT 8233 lt 8227	PDF
GAL6001 Abstract: GAL6001B-30LJ GAL6001B-30LP Text: GAL6001 High Performance E2CMOS FPLA Generic Array Logic Features Functional Block Diagram • HIGH PERFORMANCE E2CMOS TECHNOLOGY — 30ns Maximum Propagation Delay — 27MHz Maximum Frequency — 12ns Maximum Clock to Output Delay — TTL Compatible 16mA Outputs	Original	GAL6001 27MHz Tested/100% 100ms) GAL6001 GAL6001B-30LJ GAL6001B-30LP	PDF
GAL6002 Abstract: MAX235 T-FLIP FLOPS maxim rs232 multiplexer Text: GAL 6002: 4-to-1 RS232 Port Multiplexer Figure 1. TxD During Single Byte Transfer Introduction The GAL6002 is the most versatile 24-pin PLD available today. Its FPLA architecture offers buried macrocells, D/E registers, programmable clocks and dedicated input	Original	RS232 GAL6002 24-pin RS-232 MAX235 T-FLIP FLOPS maxim rs232 multiplexer	PDF
lt 8232 Abstract: LT 8215 lt 8219 lt 8239 LT 8209 lt 8217 lt 8227 lt 8220 LT 8233 lt 8221 Text: GAL6002 High Performance E2CMOS FPLA Generic Array Logic Features Functional Block Diagram ICLK • HIGH PERFORMANCE E2CMOS TECHNOLOGY — 15ns Maximum Propagation Delay — 75MHz Maximum Frequency — 6.5ns Maximum Clock to Output Delay — TTL Compatible 16mA Outputs	Original	GAL6002 75MHz Tested/100% 100ms) lt 8232 LT 8215 lt 8219 lt 8239 LT 8209 lt 8217 lt 8227 lt 8220 LT 8233 lt 8221	PDF
8256 ap Abstract: No abstract text available Text: Lattice GAL6002B High Performance E2CMOS FPLA Generic Array Logic FEATURES FUNCTIONAL BLOCK DIAGRAM • HIGH PERFORMANCE ECMOS TECHNOLOGY — 15ns Maximum Propagation Delay — 75MHz Maximum Frequency — 6.5ns Max. Clock to Output Delay — TTL Compatible 16mA Outputs	OCR Scan	GAL6002B 75MHz 100ms) 8256 ap	PDF
GAL6002 Abstract: MAX235 Text: GAL 6002: 4-to-1 RS232 Port Multiplexer Figure 1. TxD During Single Byte Transfer Introduction The GAL6002 is the most versatile 24-pin PLD available today. Its FPLA architecture offers buried macrocells, D/E registers, programmable clocks and dedicated input	Original	RS232 GAL6002 24-pin RS-232 MAX235	PDF
Untitled Abstract: No abstract text available Text: Lattice GAL6001 High Performance E2CMOS FPLA Generic Array Logic FEATURES FUNCTIONAL BLOCK DIAGRAM • HIGH PERFORMANCE ECMOS TECHNOLOGY — 30ns Maximum Propagation Delay — 27MHz Maximum Frequency — 12ns Max. Clock to Output Delay — TTL Compatible 16mA Output«	OCR Scan	GAL6001 27MHz 100ms) GAL6001JEDEC 800FASTGAL;	PDF
RT 8206 Abstract: GAL6001 GAL6001B-30LP Text: GAL6001 Lattice! High Performance E2CMOS FPLA v Generic Array Logic FUNCTIONAL BLOCK DIAGRAM • HIGH PERFORMANCE E2CMOS TECHNOLOGY — — — — — 30ns Maximum Propagation Delay 27MHz Maximum Frequency 12ns Max. Clock to Output Delay TTL Compatible 16mA Outputs	OCR Scan	GAL6001 27MHz 100ms) RT 8206 GAL6001B-30LP	PDF

FPLA APPLICATIONS Search Results

FPLA APPLICATIONS Result Highlights (5)

FPLA APPLICATIONS Datasheets Context Search

22V10

Untitled

PEEL programming

1B60

AL6002

AL6002

lt 8224

lt 8232

GAL6001

GAL6001

273-12/PEELT273-15

Untitled

ta 8221 H

lt 8232

signetics 82s100

GAL6001-30P

LT 8232

GAL6001

GAL6002

lt 8232

8256 ap

GAL6002

Untitled

RT 8206