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    FLIP FLOP COUNTER Search Results

    FLIP FLOP COUNTER Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    74ACT11175DW Rochester Electronics LLC D Flip-Flop, Visit Rochester Electronics LLC Buy
    SN54LS107J Rochester Electronics LLC J-K Flip-Flop Visit Rochester Electronics LLC Buy
    MC2125FB2 Rochester Electronics LLC MC2125 - J-K Flip-Flop Visit Rochester Electronics LLC Buy
    MM74C93N Rochester Electronics LLC Binary Counter, Visit Rochester Electronics LLC Buy
    74F779PC Rochester Electronics LLC Binary Counter, Visit Rochester Electronics LLC Buy

    FLIP FLOP COUNTER Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    DM74ALS174N

    Abstract: 74ALS175 DM74ALS174 DM74ALS174M DM74ALS174SJ DM74ALS175 DM74ALS175M M16A M16D N16A
    Text: DM74ALS174 DM74ALS175 Hex Quad D Flip-Flop with Clear General Description Features These positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic Both have an asynchronous clear input and the quad 175 version features complementary outputs from each flip-flop


    Original     		PDF DM74ALS174 DM74ALS175 DM74ALS174N 74ALS175 DM74ALS174M DM74ALS174SJ DM74ALS175 DM74ALS175M M16A M16D N16A

    MM74C74N

    Abstract: AN-90 M14A MM74C74 MM74C74M MS-001 N14A
    Text: Revised January 1999 MM74C74 Dual D-Type Flip-Flop General Description • High noise immunity: The MM74C74 dual D-type flip-flop is a monolithic complementary MOS CMOS integrated circuit constructed with N- and P-channel enhancement transistors. Each flip-flop


    Original     		PDF MM74C74 MM74C74 MM74C74N AN-90 M14A MM74C74M MS-001 N14A

    C1995

    Abstract: DM74ALS DM74ALS109A DM74ALS109AM DM74ALS109AN LS109 M16A N16A
    Text: DM74ALS109A Dual J-K PositiveEdge-Triggered Flip-Flop with Preset and Clear General Description Features The DM54ALS109A is a dual edge-triggered flip-flop Each flip-flop has individual J K clock clear and preset inputs and also complementary Q and Q outputs


    Original     		PDF DM74ALS109A DM54ALS109A C1995 DM74ALS DM74ALS109AM DM74ALS109AN LS109 M16A N16A

    DM74ALS

    Abstract: DM74ALS109A DM74ALS109AM DM74ALS109AN LS109 M16A N16A DM74ALS109
    Text: DM74ALS109A Dual J-K Positive-Edge-Triggered Flip-Flop with Preset and Clear General Description Features The DM54ALS109A is a dual edge-triggered flip-flop. Each flip-flop has individual J, K, clock, clear and preset inputs, and also complementary Q and Q outputs.


    Original     		PDF DM74ALS109A DM54ALS109A DM74ALS DM74ALS109A DM74ALS109AM DM74ALS109AN LS109 M16A N16A DM74ALS109

    CD4013BC

    Abstract: CD4013BCM CD4013BCN specifications CD4013BCN 74LS CD4013B CD4013BCSJ M14A M14D N14A
    Text: CD4013BC Dual D-Type Flip-Flop October 1987 Revised March 2002 CD4013BC Dual D-Type Flip-Flop General Description Features The CD4013B dual D-type flip-flop is a monolithic complementary MOS CMOS integrated circuit constructed with N- and P-channel enhancement mode transistors. Each


    Original     		PDF CD4013BC CD4013BC CD4013B CD4013BCM CD4013BCN specifications CD4013BCN 74LS CD4013BCSJ M14A M14D N14A

    DM74ALS109A

    Abstract: DM74ALS109AM DM74ALS109AN LS109 M16A MS-001 N16E
    Text: Revised February 2000 DM74ALS109A Dual J-K Positive-Edge-Triggered Flip-Flop with Preset and Clear General Description Features The DM74ALS109A is a dual edge-triggered flip-flop. Each flip-flop has individual J, K, clock, clear and preset inputs, and also complementary Q and Q outputs.


    Original     		PDF DM74ALS109A DM74ALS109A DM74ALS109AM DM74ALS109AN LS109 M16A MS-001 N16E

    CD4013BCN specifications

    Abstract: 74LS CD4013B CD4013BC CD4013BCM CD4013BCN CD4013BCSJ M14A M14D N14A
    Text: Revised January 1999 CD4013BC Dual D-Type Flip-Flop General Description Features The CD4013B dual D-type flip-flop is a monolithic complementary MOS CMOS integrated circuit constructed with N- and P-channel enhancement mode transistors. Each flip-flop has independent data, set, reset, and clock inputs


    Original     		PDF CD4013BC CD4013B CD4013BCN specifications 74LS CD4013BC CD4013BCM CD4013BCN CD4013BCSJ M14A M14D N14A

    CD4013B

    Abstract: CD4013BC 74LS C1995 CD4013BCJ CD4013BM CD4013BMJ CD4013BMN J14A B11b3
    Text: CD4013BM CD4013BC Dual D Flip-Flop General Description Features The CD4013B dual D flip-flop is a monolithic complementary MOS CMOS integrated circuit constructed with N- and P-channel enhancement mode transistors Each flip-flop has independent data set reset and clock inputs and ‘‘Q’’


    Original     		PDF CD4013BM CD4013BC CD4013B 74LS C1995 CD4013BCJ CD4013BMJ CD4013BMN J14A B11b3

    cd4013bcn

    Abstract: CD4013BM 74LS C1995 CD4013B CD4013BC CD4013BCJ CD4013BMJ CD4013BMN J14A
    Text: CD4013BM CD4013BC Dual D Flip-Flop General Description Features The CD4013B dual D flip-flop is a monolithic complementary MOS CMOS integrated circuit constructed with N- and P-channel enhancement mode transistors Each flip-flop has independent data set reset and clock inputs and ‘‘Q’’


    Original     		PDF CD4013BM CD4013BC CD4013B cd4013bcn 74LS C1995 CD4013BCJ CD4013BMJ CD4013BMN J14A

    MHTL

    Abstract: "J-K Flip flop" LANSDALE SEMICONDUCTOR ML688T MC688T
    Text: ML688T Dual J-K Flip-Flop Legacy Device: Motorola MC688T The negative–edge–clocked dual J-K flip-flop operates on the master–slave principle. His device provides both SET and RESET inputs on both flip-flops in the package. Each flip-flop may be set or reset by applying a low level to that particular


    Original     		PDF ML688T MC688T MHTL "J-K Flip flop" LANSDALE SEMICONDUCTOR ML688T MC688T

    MC100EL35

    Abstract: k 3555 HEL35 KL35 MC10EL35
    Text: MC10EL35, MC100EL35 5V ECL JK Flip-Flop Description The MC10EL/100EL35 is a high speed JK flip-flop. The J/K data enters the master portion of the flip-flop when the clock is LOW and is transferred to the slave, and thus the outputs, upon a positive transition


    Original     		PDF MC10EL35, MC100EL35 MC10EL/100EL35 MC10EL35/D MC100EL35 k 3555 HEL35 KL35 MC10EL35

    MM74C74N

    Abstract: AN-90 M14A MM74C74 MM74C74M MS-001 N14A
    Text: Revised May 2002 MM74C74 Dual D-Type Flip-Flop General Description Features The MM74C74 dual D-type flip-flop is a monolithic complementary MOS CMOS integrated circuit constructed with N- and P-channel enhancement transistors. Each flip-flop has independent data, preset, clear and clock inputs and Q


    Original     		PDF MM74C74 MM74C74 MM74C74N AN-90 M14A MM74C74M MS-001 N14A

    HEL35

    Abstract: MC100EL35 KL35 MC10EL35 KEL35 transistor k 4110
    Text: MC10EL35, MC100EL35 5V ECL JK Flip-Flop Description The MC10EL/100EL35 is a high speed JK flip-flop. The J/K data enters the master portion of the flip-flop when the clock is LOW and is transferred to the slave, and thus the outputs, upon a positive transition


    Original     		PDF MC10EL35, MC100EL35 MC10EL/100EL35 MC10EL35/D HEL35 MC100EL35 KL35 MC10EL35 KEL35 transistor k 4110

    40CMOS

    Abstract: No abstract text available
    Text: MM54C74,MM74C74 MM54C74 MM74C74 Dual D Flip-Flop Literature Number: SNOS336A MM54C74 MM74C74 Dual D Flip-Flop General Description The MM54C74 MM74C74 dual D flip-flop is a monolithic complementary MOS CMOS integrated circuit constructed with N- and P-channel enhancement transistors Each flipflop has independent data preset clear and clock inputs


    Original     		PDF MM54C74 MM74C74 MM74C74 SNOS336A 40CMOS

    ALS74A

    Abstract: DM74ALS74AN DM74ALS74A DM74ALS74AM DM74ALS74ASJ LS74 M14A M14D N14A dm74als74am fairchild
    Text: DM74ALS74A Dual D Positive-Edge-Triggered Flip-Flop with Preset and Clear General Description Features The ’ALS74A contains two independent positive edge-triggered flip-flops. Each flip-flop has individual D, clock, clear and preset inputs, and also complementary Q


    Original     		PDF DM74ALS74A ALS74A DM74ALS74AN DM74ALS74A DM74ALS74AM DM74ALS74ASJ LS74 M14A M14D N14A dm74als74am fairchild

    MC100E131

    Abstract: MC100E131FN MC100E131FNR2 MC10E131 MC10E131FN MC10E131FNR2
    Text: MC10E131, MC100E131 5V ECL 4-Bit D Flip-Flop The MC10E/100E131 is a quad master-slave D-type flip-flop with differential outputs. Each flip-flop may be clocked separately by holding Common Clock CC LOW and using the Clock Enable (CE) inputs for clocking. Common clocking is achieved by holding the CE


    Original     		PDF MC10E131, MC100E131 MC10E/100E131 MC10E131/D MC100E131 MC100E131FN MC100E131FNR2 MC10E131 MC10E131FN MC10E131FNR2

    Untitled

    Abstract: No abstract text available
    Text: MC10E131, MC100E131 5V ECL 4-Bit D Flip-Flop Description The MC10E/100E131 is a quad master-slave D-type flip-flop with differential outputs. Each flip-flop may be clocked separately by holding Common Clock CC LOW and using the Clock Enable (CE) inputs for clocking. Common clocking is achieved by holding the CE


    Original     		PDF MC10E131, MC100E131 MC10E/100E131 MC10E131/D

    CI 74C

    Abstract: AN-90 MM54C74 MM74C74 MM54C74J
    Text: February 1988 MM54C74/MM74C74 Dual D Flip-Flop General Description The MM54C74/MM74C74 dual D flip-flop is a monolithic complementary MOS CMOS integrated circuit constructed with N- and P-channel enhancement transistors. Each flip­ flop has independent data, preset, clear and clock inputs


    OCR Scan     		PDF MM54C74/MM74C74 CI 74C AN-90 MM54C74 MM74C74 MM54C74J

    COMPLEMENTA

    Abstract: cd4013bm
    Text: CD4013BM/CD4013BC National ÆjÉ Semiconductor CD4013BM/CD4013BC Dual D Flip-Flop General Description Features The CD4013B dual D flip-flop is a monolithic complementa­ ry MOS CMOS integrated circuit constructed with N- and P-channel enhancement mode transistors. Each flip-flop


    OCR Scan     		PDF CD4013BM/CD4013BC CD4013BM/CD4013BC CD4013B COMPLEMENTA cd4013bm

    Untitled

    Abstract: No abstract text available
    Text: m jé National Semiconductor DM74AS109 Dual J-K Positive-Edge-Triggered Flip-Flop with Preset and Clear General Description Features The ’AS109 is a dual edge-triggered flip-flop. Each flip-flop has individual J, K, clock, clear and preset inputs, and also


    OCR Scan     		PDF DM74AS109 AS109

    Untitled

    Abstract: No abstract text available
    Text: December 1989 Semiconductor DM74ALS109A Dual J-K PositiveEdge-Triggered Flip-Flop with Preset and Clear General Description Features The DM54ALS109A is a dual edge-triggered flip-flop. Each flip-flop has individual J, K, clock, clear and preset inputs, and also complementary Q and Q outputs.


    OCR Scan     		PDF DM74ALS109A DM54ALS109A

    Untitled

    Abstract: No abstract text available
    Text: 109 A National Semiconductor DM74ALS109A Dual J-K PositiveEdge-Triggered Flip-Flop with Preset and Clear General Description Features The DM54ALS109A is a dual edge-triggered flip-flop. Each flip-flop has individual J, K, clock, clear and preset inputs, and also complementary Q and Q outputs.


    OCR Scan     		PDF DM74ALS109A DM54ALS109A

    Untitled

    Abstract: No abstract text available
    Text: February 1988 CD4013BM/CD4013BC Dual D Flip-Flop General Description Features The CD4013B dual D flip-flop is a monolithic complementa­ ry MOS CMOS integrated circuit constructed with N- and P-channel enhancement mode transistors. Each flip-flop has independent data, set, reset, and clock inputs and “ Q ”


    OCR Scan     		PDF CD4013BM/CD4013BC CD4013B

    DM54ALS174J

    Abstract: DM54ALS175J 54ALS175 54als174
    Text: National Juâ Semiconductor DM54ALS174/DM54ALS175/DM74ALS174/DM74ALS175 Hex/Quad D Flip-Flop with Clear General Description Features These positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic. Both have an asynchro­


    OCR Scan     		PDF 54ALS174/DM54ALS175/DM74ALS174/DM74ALS175 DM74ALS174 ALS174 ALS175 DM54ALS174J DM54ALS175J 54ALS175 54als174