CY7C4255
Abstract: CY7C4265 CY7C42X5
Text: CY7C4255 CY7C4265 8K/16K x 18 Deep Sync FIFOs Features are 18 bits wide and are pin/functionally compatible to the CY7C42X5 Synchronous FIFO family. The CY7C4255/65 can be cascaded to increase FIFO depth. Programmable features include Almost Full/Almost Empty flags. These FIFOs provide
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CY7C4255
CY7C4265
8K/16K
CY7C42X5
CY7C4255/65
CY7C4255)
CY7C4265)
100-MHz
10-ns
CY7C4255
CY7C4265
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C4558
Abstract: C4554 C4557 c455 CY7C455-14JI CY7C455 CY7C456 CY7C457 CY7C447
Text: CY7C455 CY7C456 CY7C457 512 x 18, 1K x 18, and 2K x 18 Cascadable Clocked FIFOs with Programmable Flags • Depth Expansion Capability • 52-pin PLCC and 52-pin PQFP Features • High-speed, low-power, first-in first-out FIFO memories • 512 x 18 (CY7C455)
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CY7C455
CY7C456
CY7C457
52-pin
CY7C455)
CY7C456)
CY7C457)
83-MHz
C4558
C4554
C4557
c455
CY7C455-14JI
CY7C455
CY7C456
CY7C457
CY7C447
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honeywell hx3000
Abstract: HX3000 RHDSP24 DSP24 mxt2416 dsp24s 405F RHtMMU24 MMU24 e01a05
Text: DSP Architectures RHtMMU24 Transform Your World TM Rad Hard triple Memory Management Unit Data Sheet X3 RESET SYSCLK EN SYSTEM CONTROL TC TCP PO ACTIVE FLAGS SYSCLK START MEMW MEMOE CCOMI CS DIR HOST INTERFACE MEMORY CONTROL CCOMR R/W RHtMMU24 CSWAP A0 A1
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RHtMMU24
MMU24,
MMU24)
DSP24
RHtMMU24-Y-75-M
DSPA-RHtMMU24DS
honeywell hx3000
HX3000
RHDSP24
mxt2416
dsp24s
405F
RHtMMU24
MMU24
e01a05
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74ALS616
Abstract: 74als61
Text: S N 54A LS616, SN 54A LS617. S N 74A LS616, SN 74A LS617 16-BIT PARALLEL ERROR DETECTION AND CORRECTION CIRCUITS D2840, APRIL 1984-REVISED SEPTEMBER 1985 • D etects and Corrects Single-Bit Errors • D etects and Flags Dual-Bit Errors S N S 4 A L S 6 1 6 . S N 5 4 A IS 6 1 7 . . J D PACKAGE
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LS616,
LS617.
LS617
16-BIT
D2840,
1984-REVISED
LS617,
74ALS616
74als61
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Untitled
Abstract: No abstract text available
Text: SN74ACT7881 1024 x 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY SCAS227C - FEBRUARY 1993 - REVISED FEBRUARY 1996 • Member of the Texas Instruments Wldebus Family • Independent Asynchronous Inputs and Outputs • Input-Ready, Output-Ready, and Half-Full Flags
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SN74ACT7881
SCAS227C
SN74ACT7882,
SN74ACT7884,
SN74ACT7811
50-pF
68-Pin
80-Pln
DO-D17
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d8253
Abstract: No abstract text available
Text: SN74AS632A 32 BIT PARALLEL ERROR DETECTION AND CORRECTION CIRCUIT D 3 3 9 7 , JAN U AR Y 1990 • Detects and Corrects Single-Bit Errors • Detects and Flags Dual-Bit Errors • Built-In Diagnostic Capability • Fast W rite and Read Cycle Processing Times
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SN74AS632A
d8253
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Untitled
Abstract: No abstract text available
Text: SN 54ALS616, S N 5 4 A L S 6 1 7 , S N 74 A LS 6 16 . S N 7 4 A L S 6 1 7 16-BIT P A R A LLE L ERROR DETECTION AN D CORRECTION CIRCUITS D 2 8 4 0 , A P R IL 1 9 8 4 - R E V IS E D M A Y 1 9 8 6 • Detects and Corrects Single-Bit Errors • Detects and Flags Dual-Bit Errors
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54ALS616,
16-BIT
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Untitled
Abstract: No abstract text available
Text: SN54ACT3641 1024 x 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY SGBS309A - AUGUST 1995 - REVISED APRIL 1998 • Free-Running CLKA and CLKB Can Be Asynchronous or Coincident • Output-Ready and Almost-Empty Flags Synchronized by CLKB • Clocked FIFO Buffering Data From Port A
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SN54ACT3641
SGBS309A
5962-9560801QYA
5962-9560801NXD
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Untitled
Abstract: No abstract text available
Text: MTE Advance Information D • SöböMSb D GG2G5 3 3f l b ■ lllir n lll MNHS January 1991 NATRA M H S M 67202 HI-REL DATA SHEET 1kX 9 CMOS PARALLEL FIFO FEATURES EMPTY, FULL AND HALF FLAGS IN SINGLE DEVICE MODE RETRANSMIT CAPABILITY BI-DIRECTIONAL APPLICATIONS
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QQQ2Q72
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Untitled
Abstract: No abstract text available
Text: electronic June 1992 M 67203 HI-REL DATA SHEET 2k X 9 CMOS PARALLEL FIFO FEATURES . FIRST-IN FIRST-OUT DUAL PORT MEMORY . FAST ACCESS TIME : 35 TO 55 ns . . EMPTY, FULL AND HALF FLAGS IN SINGLE DEVICE MODE WIDE TEMPERATURE RANGE : - 55°C TO + 125°C . RETRANSMIT CAPABILITY
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67201A
Abstract: No abstract text available
Text: T em ic M67201A/M67202A S e m i c o n d u c t o r s 512 x 9 & 1 K x 9 CMOS Parallel FIFO Introduction T he M 67201A /202A im plem ent a first-in first-out algorithm , featuring asynchronous read/w rite operations. T he FU LL and E M PTY flags prevent data overflow and
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M67201A/M67202A
7201A
/202A
67201A
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4AC17
Abstract: texas instruments fifo cascaded SN74ACT7808
Text: SN74ACT7808 2048 x 9 STROBED FIRST-IN, FIRST-OUT MEMORY _SCAS205B - FEBRUARY 1991 - REVISED SEPTEMBER 1995 Load Clocks and Unload Clocks Can Be Asynchronous or Coincident * 2048 Words by 9 Bits • Expansion Logic for Depth Cascading 9 Empty, Full, and Half-Full Flags
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SN74ACT7808
2048-word
4AC17
texas instruments fifo cascaded
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CI 7473
Abstract: A10C SN74ABT7819
Text: SN74ABT7819 512 x 18 x 2 CLOCKED FIRST-IN, FIRST-OUT MEMORY SCBS125B —JULY 1992 - REVISED AUGUST 1934 Microprocessor Interface Control Logic Programmable Almost-Full/Almost-Empty Flags Fast Access Times of 9 ns With a 50-pF Load and Simultaneous Switching Data
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SN74ABT7819
SCBS125B
50-pF
80-Pin
bl723
CI 7473
A10C
SN74ABT7819
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Untitled
Abstract: No abstract text available
Text: 552 54F/74F552 Connection Diagrams Octal Registered Transceiver W ith Parity and Flags b4 b5 Description T T □ : ~28~1 b 3 Œ 27] Be □ l T h e 'F 5 5 2 o c ta l tra n s c e iv e r c o n ta in s tw o 8 -b it re g is te rs fo r te m p o ra ry b7 [ T s to ra g e o f d a ta flo w in g in e ith e r d ire c tio n . E ach re g is te r h a s its o w n c lo c k
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54F/74F552
54F/74F
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LA 7804 ON
Abstract: ci LA 7804 ON SN74ACT7804 SN74ALVC7804 W256
Text: SN74ALVC7804 512x18 FIRST-IN, FIRST-OUT MEMORY SCAS432 - JANUARY 1995 DL PACKAGE TOP VIEW • Operates at 3-V to 3.6-V V c c * Load Clock and Unload Clock Can Be Asynchronous or Coincident RESET [ 1 • Low-Power Advanced CMOS Technology D17 [ 2 * Full, Empty, and Half-Full Flags
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SN74ALVC7804
512x18
SCAS432
50-pF
SN74ACT7804
300-mil
25-mil
18-biternal
LA 7804 ON
ci LA 7804 ON
SN74ACT7804
W256
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7204A
Abstract: No abstract text available
Text: a Am7205A Advanced Micro Devices High Density First-In First-Out FIFO 8192 x 9-Bit CMOS Memory DISTINCTIVE CHARACTERISTICS • RAM based FIFO ■ Status flags—full, half-full, empty ■ 8192 x 9 organization ■ Cycle times of 25/35/45 ns for standard
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Am7205A
14191C
7204A
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AM7202
Abstract: No abstract text available
Text: A d v a n c e In f o r m a t i o n Advanced Micro Devices Am7202-40/50/65/80 High Density First-in First-out FIFO 1024x9 CM O S Memory DISTINCTIVE CHARACTERISTICS • RAM based FIFO Status flags - full, half-full, empty • 1024x9 organization Retransmit capability
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Am7202-40/50/65/80
1024x9
Am7202
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AM7203
Abstract: No abstract text available
Text: Advance Information a Advanced Micro Devices Am7203-40/50/65/80 High Density First-in First-out FIFO 2048x9 CMOS Memory DISTINCTIVE CHARACTERISTICS • RAM based FIFO Status flags - full, half-full, empty • 2048x9 organization Retransmit capability • Cycle times of 50/65/80/100 nanoseconds
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Am7203-40/50/65/80
2048x9
Am7203
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2901c
Abstract: processor Am2901 2901B AM2902 i345 AM-201C
Text: Am2901B/Am2901C A m 2 9 0 1 B /A m 2 9 0 lC Four-Bit Bipolar Microprocessor Slice DISTINCTIVE CHARACTERISTICS Left/right shift Independent of ALU Add and shift operations take only one cycle. Four status flags Carry, overflow, zero, and negative. Flexible data source selection ALU data is selected from five source ports for a total of
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Am2901B/Am2901C
Am2901s
Am2901
Am2900
01656B
2901c
processor Am2901
2901B
AM2902
i345
AM-201C
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Untitled
Abstract: No abstract text available
Text: IDT70825S/L HIGH SPEED 128K 8K X 16 BIT SEQUENTIAL ACCESS RANDOM ACCESS MEMORY (SARAM ) F e a tu re s ♦ ♦ ♦ ♦ * High-speed access * - M ilitary: 35/45ns (max.) - Com m ercial: 20/25/35/45ns (max.) Low-power operation - ID T70825S - A ddress based flags fo r b u ffer control
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IDT70825S/L
35/45ns
20/25/35/45ns
T70825S
80-pin
84-pin
MIL-PRF-38535
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Untitled
Abstract: No abstract text available
Text: 64K X 9/128K x 9 CMOS PARALLEL IN-OUT FIFO MODULE PRELIMINARY IDT7M208 IDT7M209 Integrated Device Technology, Inc. FEATURES: • • • • • • • • • device uses Full and Empty flags as warnings for data over flow and underflow conditions and expansion logic to allow for
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9/128K
IDT7M208
IDT7M209
7M208
7M209
G17bc
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Untitled
Abstract: No abstract text available
Text: Integrated Device Technology. Inc C M O S PARALLEL FIR ST-IN/FIRST-O UT FIFO 8K x 9-BIT advance in fo r ^ ion 1017205 FEATURES: DESCRIPTION: • • • • • • • • • • • • • • The IDT7205 is a dual-port memory that utilizes a special FirstIn/First-Out algorithm that loads and empties data on a first-in/firstout basis. The device uses Full and Empty flags to prevent data
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IDT7205
IDT7200/01/02/03/04
28-pin
32-pin
MIL-STD-883,
DSC-2006/-
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Untitled
Abstract: No abstract text available
Text: CMOS ASYNCHRONOUS FIFO 65,536 X 9 ADVANCED INFORMATION IDT7208 Integrated Device Technology, Inc. internal pointers that load and empty data on a first-in/first-out basis. The device uses Full and Empty flags to prevent data overflow and underflow and expansion logic to allow for
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IDT7208
IDT7208
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Untitled
Abstract: No abstract text available
Text: HIGH-SPEED 3.3V 32K x 16 BANK-SWITCHABLE DUAL-PORTED SRAM WITH EXTERNAL BANK SELECTS PRELIMINARY IDT70V7278S/L Features 32K x 16 Bank-Switchable Dual-Ported SRAM Architecture * processor communications; interrupt option Interrupt flags with programmable masking
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IDT70V7278S/L
100-pin
16-bit
eac16
MO-136,
492-M
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