XMega 256
Abstract: AVR 32BIT avr instruction set XMEGA Application Notes
Text: Instruction Set Nomenclature Status Register SREG SREG: Status Register C: Carry Flag Z: Zero Flag N: Negative Flag V: Two’s complement overflow indicator S: N ⊕ V, For signed tests H: Half Carry Flag T: Transfer bit used by BLD and BST instructions
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0856H
XMega 256
AVR 32BIT
avr instruction set
XMEGA Application Notes
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avr microcontroller
Abstract: AT90S1200 avr instruction set summary
Text: Instruction Set Nomenclature Status Register SREG SREG: Status Register C: Carry Flag Z: Zero Flag N: Negative Flag V: Two’s complement overflow indicator S: N ⊕ V, For signed tests H: Half Carry Flag T: Transfer bit used by BLD and BST instructions
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0856D
avr microcontroller
AT90S1200
avr instruction set summary
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0856D-AVR-08
Abstract: avr instruction sets in assembler AT90S1200
Text: Instruction Set Nomenclature Status Register SREG SREG: Status Register C: Carry Flag Z: Zero Flag N: Negative Flag V: Two’s complement overflow indicator S: N ⊕ V, For signed tests H: Half Carry Flag T: Transfer bit used by BLD and BST instructions
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0856D
0856D-AVR-08
avr instruction sets in assembler
AT90S1200
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Mnemonics
Abstract: avr instruction set XMEGA Application Notes
Text: Instruction Set Nomenclature Status Register SREG SREG: Status Register C: Carry Flag Z: Zero Flag N: Negative Flag V: Two’s complement overflow indicator S: N ⊕ V, For signed tests H: Half Carry Flag T: Transfer bit used by BLD and BST instructions
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0856I
Mnemonics
avr instruction set
XMEGA Application Notes
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avr microcontroller
Abstract: AT90S1200
Text: Instruction Set Nomenclature Status Register SREG SREG: Status register C: Carry flag Z: Zero flag N: Negative flag V: Two’s complement overflow indicator S: N ⊕ V, For signed tests H: Half Carry flag T: Transfer bit used by BLD and BST instructions
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0856C
avr microcontroller
AT90S1200
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0856E
Abstract: AT90S1200 AVR instruction set
Text: Instruction Set Nomenclature Status Register SREG SREG: Status Register C: Carry Flag Z: Zero Flag N: Negative Flag V: Two’s complement overflow indicator S: N ⊕ V, For signed tests H: Half Carry Flag T: Transfer bit used by BLD and BST instructions
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0856E
AT90S1200
AVR instruction set
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program counter
Abstract: SEV 1011 BRGE1
Text: Instruction Set Nomenclature: Status Register SREG SREG: Status register C: Carry flag in status register Z: Zero flag in status register N: Negative flag in status register V: Two’s complement overflow indicator S: N ⊕ V, For signed tests H: Half Carry flag in the status register
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0856B
06/99/xM
program counter
SEV 1011
BRGE1
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avr instruction sets in assembler
Abstract: 77lds 00kk RD16D
Text: Instruction Set Nomenclature: Status Register SREG SREG: Status register C: Carry flag in status register Z: Zero flag in status register N: Negative flag in status register V: Two’s complement overflow indicator S: N ⊕ V, For signed tests H: Half Carry flag in the status register
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0856B
06/99/xM
avr instruction sets in assembler
77lds
00kk
RD16D
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AT90S
Abstract: AT94K atmel AT94K
Text: 2-wire Serial Macros Features: • • • • • • Setting the 2-wire Serial Bit Rate Register Clearing the 2-wire Serial Interrupt Flag Enabling/Disabling the 2-wire Serial Acknowledge Flag Asserting the 2-wire Serial Stop Condition Flag Enabling/Disabling the 2-wire Serial Interface Flag
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AT94K
04/01/xM
AT90S
atmel AT94K
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00KK
Abstract: RD16D
Text: Instruction Set Instruction Set Nomenclature: Status Register SREG : SREG: Status register C: Carry flag in status register Z: Zero flag in status register N: Negative flag in status register V: Twos complement overflow indicator S: N ⊕ V, For signed tests
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alarm clock 8051 microcontroller
Abstract: DS80C310 DS80C320 DS80C323 DS83C520 DS87C520 DS87C530 80C52
Text: HIGH–SPEED MICROCONTROLLER USER’S GUIDE SECTION 3: ARCHITECTURE eral Purpose Flag, Register Bank Select, Overflow Flag, and Parity Flag. The High–Speed Microcontroller is based on the industry standard 80C52. The core is an accumulator based architecture using internal registers for data storage and
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80C52.
alarm clock 8051 microcontroller
DS80C310
DS80C320
DS80C323
DS83C520
DS87C520
DS87C530
80C52
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ADSP-21XXX
Abstract: rfft2048 ADSP-21000 ADSP-21020 ADSP-21060 CB15
Text: 3 Title poll_flag_in test input flag FUNCTION poll_flag_in—test input flag SYNOPSIS #include <21020.h> or <21060.h> int poll_flag_in int flag, int mode ; DESCRIPTION This function is an Analog Devices extension to the ANSI standard. The poll_flag_in function tests the specified flag (0, 1, 2, 3) for the
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GPL16925X
Abstract: 0x5555 VDDO33 timebase IC GPL169251A GPL169256UA conclusion AN007
Text: AN0075 GPL16925X Oct. 13, 2009 Reset Flag Register Mistakenly Clearance Issue Introduction Reset flag register 0x7006 will be mistakenly cleared when writing to system clock control register, 0x7007. Analysis When program writes data to system clock control register 0x7007, this data will also be written to reset flag
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AN0075
GPL16925X
0x7006
0x7007.
0x7007,
32768Hz;
245ms
GPL16925X
0x5555
VDDO33
timebase IC
GPL169251A
GPL169256UA
conclusion
AN007
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8051 instruction set
Abstract: intel 8051 INSTRUCTION SET 8051 opcode 8051 simple program Atmel 8051 Microcontrollers bit address for i/o and ram by 8051 instruction set of 8051 intel 8051 opcode sheet 80C51 AT89
Text: Section 1 80C51 Microcontrollers Instruction Set For interrupt response time information, refer to the hardware description chapter. Instructions that Affect Flag Settings 1 Instruction Flag Instruction Flag C OV AC ADD X X X CLR C O ADDC X X X CPL C X SUBB
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80C51
8051 instruction set
intel 8051 INSTRUCTION SET
8051 opcode
8051 simple program
Atmel 8051 Microcontrollers
bit address for i/o and ram by 8051
instruction set of 8051
intel 8051 opcode sheet
AT89
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intel 8051 INSTRUCTION SET
Abstract: 8051 instruction set instruction set of 8051 AT89 R67D
Text: Instruction Set Microcontroller Instruction Set For interrupt response time information, refer to the hardware description chapter. 1 Instructions that Affect Flag Settings Instruction Flag Instruction Flag C OV AC ADD X X X CLR C O ADDC X X X CPL C X SUBB
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Untitled
Abstract: No abstract text available
Text: Errata • • • • Wrong Clearing of XTRF in MCUSR Reset During EEPROM Write Verifying EEPROM in System Serial programming at voltages below 3.0 Volts 4. Wrong Clearing of XTRF in MCUSR The XTRF flag in MCUSR will be cleared when clearing the PORF-flag. The flag
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1192B
01/99/xM
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eb 102H
Abstract: AT89 0345H
Text: Microcontroller Instruction Set For interrupt response time information, refer to the hardware description chapter. Instructions that Affect Flag Settings 1 Instruction Flag Instruction Flag C OV AC ADD X X X CLR C O ADDC X X X CPL C X SUBB X X X ANL C,bit
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54ACT11853
Abstract: 74ACT11853
Text: 54ACT11853, 74ACT11853 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS SCAS389 – MARCH 1990 • • • • • • • • • High-Speed Bus Transceivers with Parity Generator/Checker Parity-Error Flag Open-Drain Output Register for Storage of the Parity Error Flag
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54ACT11853,
74ACT11853
SCAS389
500-mA
300-mil
ACT11853
54ACT11853
74ACT11853
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54AC11833
Abstract: 74AC11833
Text: 54AC11833, 74AC11833 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS SCAS387 – MARCH 1990–REVISED OCTOBER 1990 • • • • • • • • High-Speed Bus Transceivers With Parity Generator/Checker Parity-Error-Flag Open-Drain Output Register for Storage of the Parity-Error Flag
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54AC11833,
74AC11833
SCAS387
500-mA
300-mil
54AC11833
74AC11833
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N74F755D
Abstract: 74F755
Text: Signetics FAST 74F755 Register FAST Products Octal MailBox Register With Ready Flag 3-State Product Specification FEATURES • Flag set on Write signal (If desired) • Automatic flag set upon Read signal TYPE • Pen collector flag status output • Flag status can be read via data
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74F755
N74F755
180MHz
24-Pin
300mil)
N74F755N
N74F755D
74F755
500ns
N74F755D
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flag register
Abstract: flag
Text: C8400 5. Flags 5.1 Bit assignment of the Flag register. The function of each bit in the Flag register is defined as below. D7 S DO z X H X P/V N C r Carry flag C Carry flag is set by carry produced by Accumulator from the MSB at execution of add instructions, sub
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C8400
flag register
flag
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N74F755
Abstract: em 6695
Text: FAST 74F755 Register FAST Products Octal MallBox Register With Ready Flag 3-State Product Specification FEATURES • Flag set on Write signal (if desired) • Automatic flag set upon Read signal TYPE T V W C A L Im a x TY PIC A L SU PPLY CU RR EN T (TOTAL)
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74F755
N74F755
180MHz
24-Pin
300mil)
N74F755N
N74F755D
74F755
500ns
em 6695
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Shared resource arbitration
Abstract: No abstract text available
Text: miMHS PRELIMINARY March 1994 L 67005 DATA SHEET 8 KX 8 CMOS DUAL PORT RAM 3.3 VOLT FEATURES VERSATILE PIN SELECT FOR MASTER OR SLAVE: - M/S= H FOR BUSY OUTPUT FLAG ON MASTER - M/S = L FOR BUSY INPUT FLAG ON SLAVE INT FLAG FOR PORT TO PORT COMMUNICATION FULL HARDWARE SUPPORT OF SEMAPHORE
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7005V
6700Sffiev
hfl45b
Shared resource arbitration
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Untitled
Abstract: No abstract text available
Text: SN74ALS29833 8-BIT TO 9-BIT PARITY BUS TRANSCEIVER SDAS119D - FEBRUARY 1987 - REVISED JANUARY 1995 Functionally Similar to AMD’s AM29833 High-Speed Bus Transceiver With Parity Generator/Checker Parlty-Error Flag With Open-Collector Outputs Register for Storing the Parity-Error Flag
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SN74ALS29833
SDAS119D
AM29833
300-mll
LS29833
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