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Amphenol LTW Technology 12-05PFIP-SF8004 M SERIES, M12, 4A, 05 PINS, RECE
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
DigiKey	12-05PFIP-SF8004	Bulk	21		1	1 $10.17 10 $8.644 100 $7.3472 1000 $6.24631 10000 $6.24631	Buy Now
Newark	12-05PFIP-SF8004	Bulk			10	1 $9.12 10 $9.12 100 $7.13 1000 $6.74 10000 $6.74	Buy Now
RS	12-05PFIP-SF8004	Bulk		10 Weeks	10	1 - 10 $8.29 100 $7.02 1000 $7.02 10000 $7.02	Get Quote
Interstate Connecting Components	12-05PFIP-SF8004					1 - 10 - 100 - 1000 - 10000 -	Buy Now
Amphenol LTW Technology 12-05PFIP-SF8003 M SERIES, M12, 4A, 05 PINS, RECE
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
DigiKey	12-05PFIP-SF8003	Bulk	20		1	1 $10.11 10 $8.594 100 $7.3051 1000 $6.21044 10000 $6.21044	Buy Now
Newark	12-05PFIP-SF8003	Bulk			10	1 $9.06 10 $9.06 100 $7.09 1000 $6.7 10000 $6.7	Buy Now
RS	12-05PFIP-SF8003	Bulk		10 Weeks	10	1 - 10 $8.24 100 $6.97 1000 $6.97 10000 $6.97	Get Quote
Interstate Connecting Components	12-05PFIP-SF8003					1 - 10 - 100 - 1000 - 10000 -	Buy Now
Finisar Corporation FIP-S-31-00-4 ISOLATOR PIGTAIL 1310NM SC/APC
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
DigiKey	FIP-S-31-00-4	Bulk			200	1 - 10 - 100 - 1000 $14.3719 10000 $14.3719	Buy Now
Finisar Corporation FIP-S-55-10-4 ISOLATOR PIGTAIL 1550NM SC/APC
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
DigiKey	FIP-S-55-10-4	Bulk			200	1 - 10 - 100 - 1000 $14.3719 10000 $14.3719	Buy Now
Intel Corporation APIG.SM.FIPS 942836 (Alt: APIG.SM.FIPS 942836)
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
Avnet Americas	APIG.SM.FIPS 942836				1	1 $114554 10 $112750 100 $107338 1000 $107338 10000 $107338	Buy Now

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FIPS Datasheets (2)

Part	ECAD Model	Manufacturer	Description	Curated	Datasheet Type	PDF
FIP-S-31-00-4		Finisar	Accessories, Optoelectronics, ISOLATOR PIGTAIL 1310NM SC/APC		Original	PDF
FIP-S-55-10-4		Finisar	Accessories, Optoelectronics, ISOLATOR PIGTAIL 1550NM SC/APC		Original	PDF

FIPS Datasheets Context Search

Catalog Datasheet	Type	Document Tags	PDF
L6590 Abstract: SO16W Text: L6590  FULLY INTEGRATED POWER SUPPLY FIPS PRODUCT PREVIEW Features WIDE-RANGE MAINS OPERATION ”ON-CHIP” 700V BVDSS POWER MOS 65kHz INTERNAL OSCILLATOR 2.5V ±2% INTERNAL REFERENCE STANDBY MODE FOR HIGH EFFICIENCY AT LIGHT LOAD OVERCURRENT AND LATCHED OVERVOLTAGE PROTECTION	Original	L6590 65kHz SO16W L6590 SO16W	PDF
verilog code for 32 bit AES encryption Abstract: FIPS-197 SP800-38A EP3C40-6 Text: AES-P Programmable AES Encrypt/Decrypt Megafunction Conforms to the Advanced Encryption Standard AES standard (FIPS PUB 197) Single module efficiently integrates multiple AES functions and modes Run-time programmable for: − Encryption or Decryption − Cipher Key length:	Original	256-bits FIPS-197 128-bit, 192-bit 256-bit verilog code for 32 bit AES encryption SP800-38A EP3C40-6	PDF
SP800-38A Abstract: FIPS-197 verilog code for 128 bit AES encryption verilog code for 32 bit AES encryption verilog code for AES algorithm verilog code for aes encryption Text: Conforms to the Advanced Encryption Standard AES standard (FIPS PUB 197) AES-C Single module efficiently integrates multiple AES functions AES Optimized Encrypt/Decrypt Core Run-time programmable for: The AES-C core implements hardware data encryption and decryption using Rijndael	Original	FIPS-197 256-bits 128ace SP800-38A verilog code for 128 bit AES encryption verilog code for 32 bit AES encryption verilog code for AES algorithm verilog code for aes encryption	PDF
verilog code for implementation of des Abstract: 3S1200E-4 verilog code for des Text: FIPS 46-3 Standard Compliant DES Data Encryption Standard Core Encryption/Decryption performed in 16 cycles ECB mode 56 bits of security For use in FPGA or ASIC designs Verilog IP Core Non Pipelined version Small gate count The DES core implements the Data Encryption Standard (DES) documented in the U.S.	Original	0x0123456789abcdef 0x4e6f772069732074 0x68652074696d6520 0x666f7220616c6c20 0x3fa40e8a984d4815 0x6a271787ab8883f9 0x893d51ec4b563b53 verilog code for implementation of des 3S1200E-4 verilog code for des	PDF
verilog code for implementation of des Abstract: verilog code for des tsmc sram des verilog RTL 604 Text: FIPS 46-3 Standard Compliant DES Data Encryption Standard Core Encryption/Decryption performed in 16 cycles ECB mode 56 bits of security For use in FPGA or ASIC designs Verilog IP Core Non Pipelined version Small gate count The DES core implements the Data Encryption Standard (DES) documented in the U.S.	Original	0x0123456789abcdef 0x4e6f772069732074 0x68652074696d6520 0x666f7220616c6c20 0x3fa40e8a984d4815 0x6a271787ab8883f9 0x893d51ec4b563b53 verilog code for implementation of des verilog code for des tsmc sram des verilog RTL 604	PDF
667 ecb Abstract: verilog code for implementation of des verilog code for des tsmc sram Text: FIPS 46-3 Standard Compliant Encryption/Decryption performed in 48 cycles ECB mode DES3 Up to 168 bits of security Triple Data Encryption Standard Core Verilog IP Core The DES3 core implements the Triple Data Encryption Standard (DES3) documented in the U.S. Government publication FIPS 46-3.	Original		PDF
Untitled Abstract: No abstract text available Text: Abridged Data Sheet DS28CN01 1Kbit I²C/SMBus EEPROM with SHA-1 Engine www.maxim-ic.com GENERAL DESCRIPTION FEATURES The DS28CN01 combines 1024 bits of EEPROM with challenge-and-response authentication security implemented with the Federal Information Publications FIPS 180-1/180-2 and ISO/IEC 101183 Secure Hash Algorithm (SHA-1). The memory is	Original	DS28CN01 DS28CN01 64-bit 300ns. 400pF 300pF	PDF
SO16 wide package Abstract: Optcoupler L6590 SO16W Text: L6590 FULLY INTEGRATED POWER SUPPLY FIPS PRODUCT PREVIEW Features WIDE-RANGE MAINS OPERATION "ON-CHIP" 700V BVDSS POWER MOS 100kHz INTERNAL OSCILLATOR 2.5V ±2% INTERNAL REFERENCE STANDBY MODE FOR HIGH EFFICIENCY AT LIGHT LOAD OVERCURRENT AND LATCHED OVERVOLTAGE PROTECTION	Original	L6590 100kHz SO16W L6590 SO16 wide package Optcoupler SO16W	PDF
Untitled Abstract: No abstract text available Text: ABRIDGED DATA SHEET DS28E15 1-Wire SHA-256 Secure Authenticator with 512-Bit User EEPROM General Description Features The DS28E15 combines crypto-strong bidirectional secure challenge-and-response authentication functionality with an implementation based on the FIPS	Original	DS28E15 SHA-256 512-Bit DS28E15 180-3-specified SHA-256) SHA256 64-bit 320pF	PDF
DS28E02 Abstract: DS28E02P TSOC CRC16 CRC-16 T633 T633-2 21038 Text: ABRIDGED DATA SHEET Rev 0: 6/10 1-Wire SHA-1 Authenticated 1Kb EEPROM with 1.8V Operation The DS28E02 combines 1024 bits of EEPROM with challenge-and-response authentication security implemented with the FIPS 180-3 Secure Hash Algorithm SHA-1 . The 1024-bit EEPROM array is configured as	Original	DS28E02 1024-bit 64-bit DS28E02 DS28E02P TSOC CRC16 CRC-16 T633 T633-2 21038	PDF
TSOC 6 Abstract: 28E22 Text: ABRIDGED DATA SHEET EVALUATION KIT AVAILABLE DS28E22 DeepCover Secure Authenticator with 1-Wire SHA-256 and 2Kb User EEPROM General Description The DS28E22 combines crypto-strong, bidirectional, secure challenge-and-response authentication functionality with an implementation based on the FIPS	Original	DS28E22 SHA-256 180-3-specified SHA-256) SHA256 64-bit TSOC 6 28E22	PDF
Untitled Abstract: No abstract text available Text: Government Security Products G83-6744 Smart Card Keyboards Full QWERTY Keyboard with Integrated FIPS 201 Certified Smart Card Reader Cable Length: • Approx. 1.75 m  Approx. 5.74 ft. Actual product may vary from picture shown USB keyboard with chipcard reader	Original	G83-6744 G83-6744. G83-6744 G83-6744LUAUS-2	PDF
Untitled Abstract: No abstract text available Text: ABRIDGED DATA SHEET 219-0008; Rev 1; 3/12 1-Wire SHA-1 Authenticated 1Kb EEPROM with 1.8V Operation The DS28E02 combines 1024 bits of EEPROM with challenge-and-response authentication security implemented with the FIPS 180-3 Secure Hash Algorithm SHA-1 . The 1024-bit EEPROM array is configured as	Original	DS28E02 1024-bit 64-bit	PDF
STM1404 Abstract: No abstract text available Text: STM1403 3 V FIPS-140 security supervisor with battery switchover Features • ■ STM1403 supports FIPS-140 security level 3+ – Four high-impedance physical tamper inputs – Over/under operating voltage detector – Security alarm SAL on tamper detection	Original	STM1403 FIPS-140 STM1403 FIPS-140 STM1403A QFN16, STM1404	PDF

BAT54J Abstract: FIPS-140 STM1403 STM1404 Text: STM1403 3 V FIPS-140 security supervisor with battery switchover Features • STM1403 supports FIPS-140 security level 3+ – Four high-impedance physical tamper inputs – Over/under operating voltage detector – Security alarm SAL on tamper detection	Original	STM1403 FIPS-140 STM1403 FIPS-140 STM1403A QFN16, 16-piand BAT54J STM1404	PDF
DP4201J Abstract: No abstract text available Text: Microprocessor Support Circuits DP4201 National Semiconductor DP4201 Clock Generator General Description Features The DP4201 C lo ck G enerator is designed fo r 4 00 4 m ic ro -c o m p u te r series fa m ily a p p lica tio n s, and satisfies c lo c k signal requ ire m e n ts M C S - 4 0 " ^ and FIPS 4 -B it	OCR Scan	DP4201 DP4201 MCS-40 DP4201J	PDF
STM1404 Abstract: 1N5817 BAT54J FIPS-140 STM1404A STM1404B STM1404C Text: STM1404 3 V FIPS-140 security supervisor with battery switchover Features • ■ ■ ■ STM1404 supports FIPS-140 security level 4 – Four high-impedance physical tamper inputs – Over/under operating voltage detector – Security alarm SAL on tamper detection	Original	STM1404 FIPS-140 STM1404 FIPS-140 QFN16, STM1404A 1N5817 BAT54J STM1404B STM1404C	PDF
Untitled Abstract: No abstract text available Text: Atmel ATECC108 Atmel CryptoAuthentication SUMMARY DATASHEET Features   Secure authentication and product validation device High-Speed Public Key Algorithm PKI Crypto Engine ○ FIPS186-3 Elliptic Curve Digital Signature Algorithm (ECDSA)   	Original	ATECC108 FIPS186-3 SHA-256 256/283-bit 72-bit	PDF
STM7007 Abstract: No abstract text available Text: STM7007 Single-chip hardware accelerated encryption engine for computer and peripherals applications Data brief Features • World class encryption engine – HardCache Crypto module – FIPS 140-2 security level 3 – NIST Certificate #1599 ■ Symmetric algorithms NIST FIPS approved	Original	STM7007 SHA-256, SHA-384 SHA-512 384-bit STM7007	PDF
DS28CN01 Abstract: No abstract text available Text: Abridged Data Sheet DS28CN01 1Kbit I²C/SMBus EEPROM with SHA-1 Engine www.maxim-ic.com GENERAL DESCRIPTION FEATURES The DS28CN01 combines 1024 bits of EEPROM with challenge-and-response authentication security implemented with the Federal Information Publications FIPS 180-1/180-2 and ISO/IEC 101183 Secure Hash Algorithm (SHA-1). The memory is	Original	DS28CN01 DS28CN01 64-bit 400pF 300pF	PDF
cbc 327 Abstract: verilog code for 128 bit AES encryption FIPS-197 SP800-38A EP3SE50 verilog code for 32 bit AES encryption verilog code for AES algorithm Text: Conforms to the Advanced Encryption Standard AES standard (FIPS PUB 197) AES-C Single module efficiently integrates multiple AES functions AES Optimized Encrypt/Decrypt Megafunction Run-time programmable for: The AES-C megafunction implements hardware data encryption and decryption using	Original	FIPS-197 128-bit, 192-bit 256-bit 32-bit SP800-38A cbc 327 verilog code for 128 bit AES encryption EP3SE50 verilog code for 32 bit AES encryption verilog code for AES algorithm	PDF
verilog code for implementation of des Abstract: Data Encryption Standard DES Text: FIPS 46-3 Standard Compliant Encryption/Decryption performed in 48 cycles ECB mode DES3 Up to 168 bits of security Triple Data Encryption Standard Megafunction Verilog IP Megafunction The DES3 megafunction implements the Triple Data Encryption Standard (DES3) documented in the U.S. Government publication FIPS 46-3.	Original		PDF
tamper detection sensors Abstract: STM1404 BLD 122 BLD-3 1N5817 BAT54J FIPS-140 STM1404A STM1404B STM1404C Text: STM1404 3V FIPS-140 Security supervisor with battery switchover Features • ■ ■ ■ STM1404 supports FIPS-140 security level 4 – Four high-impedance physical tamper inputs – Over/Under operating voltage detector – Security alarm SAL on tamper detection	Original	STM1404 FIPS-140 STM1404 FIPS-140 QFN16, STM1404A tamper detection sensors BLD 122 BLD-3 1N5817 BAT54J STM1404B STM1404C	PDF
3S500E-5 Abstract: sha1 verilog code for sha1 hash function Text:  Compliant to the FIPS 180-1 specification for SHA-1.  Bit padding. SHA1 SHA-1 Secure Hash Function Core  264-1 bits maximum message length.  Supported Message lengths mul- tiple of 8-bits.  Initial values of Chaining Va- riables selected before	Original		PDF

FIPS Search Results

FIPS Price and Stock

Amphenol LTW Technology 12-05PFIP-SF8004

Amphenol LTW Technology 12-05PFIP-SF8003

Finisar Corporation FIP-S-31-00-4

Finisar Corporation FIP-S-55-10-4

Intel Corporation APIG.SM.FIPS 942836

FIPS Datasheets (2)

FIPS Datasheets Context Search

L6590

verilog code for 32 bit AES encryption

SP800-38A

verilog code for implementation of des

verilog code for implementation of des

667 ecb

Untitled

SO16 wide package

Untitled

DS28E02

TSOC 6

Untitled

Untitled

STM1404

BAT54J

DP4201J

STM1404

Untitled

STM7007

DS28CN01

cbc 327

verilog code for implementation of des

tamper detection sensors

3S500E-5