idt54
Abstract: S101-05 S10-171 74FCT821CT
Text: i f dt) IntegratedDeviceTechnotosyInc ADVANCE INFORMATION FCTXXXCT TTL OUTPUT ONLY SERIES HIGH-SPEED CMOS LOGIC FEATURES: DESCRIPTION: • FCTXXXCT series 25% faster than FCTAT speeds • CMOS devices with TRUE TTL input and output com patibility The FCTXXXCT is a high-speed CMOS logic family designed
|
OCR Scan
|
S10-5
idt54
S101-05
S10-171
74FCT821CT
|
PDF
|
Untitled
Abstract: No abstract text available
Text: SC1302A/B/C/D/E/F Dual High Speed Low-Side MOSFET Driver POWER MANAGEMENT Features Description The SC1302A/B/C/D/E/F family are low cost dual low-side MOSFET drivers. These drivers accept TTL-compatible inputs and are capable of supplying high current outputs
|
Original
|
SC1302A/B/C/D/E/F
1000pf
SC1302A/B/C/D/E/F
IPC-SM-782A,
|
PDF
|
SC1302A
Abstract: SC1302B SC1302C
Text: SC1302A/B/C/D/E/F Dual High Speed Low-Side MOSFET Driver POWER MANAGEMENT Features Description The SC1302A/B/C/D/E/F family are low cost dual low-side MOSFET drivers. These drivers accept TTL-compatible inputs and are capable of supplying high current outputs
|
Original
|
SC1302A/B/C/D/E/F
1000pf
SC1302A/B/C/D/E/F
MS-012,
IPC-SM-782A,
SC1302A
SC1302B
SC1302C
|
PDF
|
TL390
Abstract: No abstract text available
Text: COM’L: -5/7/B/B-2/A, 10/2 F IN A L PAL20R8 Family AdvaH niccero 24-Pin TTL Programmable Array Logic Devices DISTINCTIVE CHARACTERISTICS • 5-ns propagation delay ■ Power-up reset for initialization ■ Popular 24-pin architectures: 20L8, 20R8, 20R6, 20R4
|
OCR Scan
|
PAL20R8
24-Pin
28-pin
PAL20L8,
PAL20R8,
PAL20R6,
PAL20R4)
TL390
|
PDF
|
PAL20LB
Abstract: mmi 20L8 amd part marking 20L8 PAL20L8 PAL20R4 PAL20R6 PAL20R8 PAL20L8-7
Text: F IN A L C O M 'L : -5 /7 /B /B -2 /A , 10/2 a Advanced Micro Devices PAL20R8 Family 24-Pin TTL Programmable Array Logic DISTINCTIVE CHARACTERISTICS • 5*ns propagation delay ■ Power-up reset for Initialization ■ Popular 24-pin architectures: 20L8,20R8,
|
OCR Scan
|
PAL20R8
24-Pin
PAL20R8.
PAL20R6,
PAL20R4)
PAL20R8-5
28-pin
PAL20LB
mmi 20L8
amd part marking
20L8
PAL20L8
PAL20R4
PAL20R6
PAL20L8-7
|
PDF
|
PAL16R8 MMI
Abstract: PAL16l8 MMI
Text: F 1N A L COM’L: -4/5/7/B/B-2/A, D/2 PAL16R8 Family AdvarS! 20-Pin TTL Programmable Array Logic Devices DISTINCTIVE CHARACTERISTICS • As fast as 4.5 ns maximum propagation delay ■ Power-up reset for initialization ■ Popular 20-pin architectures: 16L8,16R 8,16R6,
|
OCR Scan
|
PAL16R8
20-Pin
28-Pin
PAL16L8,
PAL16R8,
PAL16R6,
PAL16R4)
PAL16R8 MMI
PAL16l8 MMI
|
PDF
|
Untitled
Abstract: No abstract text available
Text: PALI 6R8 Family F eatures/B enefits 16L8,16R8 16R6,16R4 Ordering Inform ation — Newer Products • Standard 20-pln architectures PALC16R8Q-25 C Q STD • TTL and CMOS versions • High speed, as test as 10 ns tPD for PAL16R8D Series PROGRAMMABLE ARRAY LOGIC
|
OCR Scan
|
20-pln
PALC16R8Q-25
PAL16R8D
PALC16R8Z
PAL16R8
|
PDF
|
Untitled
Abstract: No abstract text available
Text: V54FCT823A V74FCT823A 9-BIT BUS INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS FCT FAMILY DATA SHEETS F EATU R ES •Direct CMOS Replacement for 29823 •Speed Equivalent to 29823 •Output Drive Equivalent to 29823 •CMOS Low Power 5nW typ. static •Outputs Compatible with both CMOS and TTL
|
OCR Scan
|
V54FCT823A
V74FCT823A
|
PDF
|
1N3064
Abstract: 1N916 TE1000 TE3000
Text: DATA SHEET Bipolar Gate Arrays TE1000 Series Gate Array DESCRIPTION The TE1000 high-speed gate array is a member o f the Customized TTL-ECL Gate Array family, designed using advanced oxil-isolated OXIL bipolar technology. It features 1000 internal gates and has a total of 96 inputs,
|
OCR Scan
|
TE1000
50-ohm
68-lead
1N916
1N3064.
68-Pin
1N3064
TE3000
|
PDF
|
Untitled
Abstract: No abstract text available
Text: ACT 2 Family FPGAs F e a tu re s • Up to 8000 Gate Array Gates 20,000 PLD equivalent gates Datapath Performance at 105 MHz • Replaces up to 200 TTL Packages • Replaces up to eighty 20-Pin PAL Packages Two In-Circuit Diagnostic Probe Pins Support Speed
|
OCR Scan
|
20-Pin
16-Bit
|
PDF
|
EP330-12CN
Abstract: EP330 EP330-15CN EP330-15C EP330-15 EP330-15CFN
Text: C D f« C C D IC C HIGH-PERFORMANCE 8-MACROCELL ONE-TIME PROGRAMMABLE LOGIC DEVICES _ SRES002A - D3374, OCTOBER 1 9 8 9 - REVISED SEPTEMBER 1992 N PACKAGE Programmable Replacement for Conventional TTL, 74HC, and 20-Pin PLD Family TOP VIEW) High-Voltage EPIC Process Allows for
|
OCR Scan
|
SRES002A
D3374,
20-Pin
EP330
EP330-12CN
EP330-15CN
EP330-15C
EP330-15
EP330-15CFN
|
PDF
|
Untitled
Abstract: No abstract text available
Text: DATA SHEET ÌÀTCT Bipolar Gate Arrays TE3000 Series Gate Array DESCRIPTION CAD FEATURES The TE3000 high-speed gate array is a member of the Customized TTL-ECL Gate Array family, designed using advanced oxil-isolated OXIL bipolar technology. It features 3000 internal gates and has a total o f 168 inputs,
|
OCR Scan
|
TE3000
50-ohm
149-lead
|
PDF
|
1N3064
Abstract: 1N916 TE1000 TE3000
Text: DATA SHEET ÌAT&T Bipolar Gate Arrays TE3000 Series Gate Array DESCRIPTION CAD FEATURES The TE3000 high-speed gate array is a member of the Customized TTL-ECL Gate Array family, designed using advanced oxil-isolated OXIL bipolar technology. It features 3000 internal gates and has a total o f 168 inputs,
|
OCR Scan
|
TE3000
50-ohm
149-lead
149-Pin
1N3064
1N916
TE1000
|
PDF
|
Untitled
Abstract: No abstract text available
Text: DATA SHEET =AT bT Bipolar Gate Arrays TE1000 Series Gate Array DESCRIPTION CAD FEATURES The TE1000 high-speed gate array is a member o f the Customized TTL-E C L Gate Array family, designed using advanced oxil-isolated OXIL bipolar technology. It features 1000 internal gates and has a total of 96 inputs,
|
OCR Scan
|
TE1000
50-ohm
68-lead
68-leaden
1N916
1N3064.
68-Pin
|
PDF
|
|
|
DS9471-R2
Abstract: MC68B00L M6800 programming manual sem 5025 MC6800P motorola M6800 MC6800 MC6800L MC6800 manual 9c4h
Text: ! M M O T O R O L A SEM IC O N DU C TO R S b _ . J E ~ I f c i \ BL ."J 8 AUST N TEXA 7 c ,'. MOS -B IT MICROPROCESSING U N IT M PU The MC6800 is a monolithic 8 -bit microprocessor forming the central control function for Motorola's M6800 family. Compatible with TTL, the
|
OCR Scan
|
MC6800
M6800
MC6800,
16-bit
MC6800/D
DS9471-R2
MC68B00L
M6800 programming manual
sem 5025
MC6800P
motorola M6800
MC6800L
MC6800 manual
9c4h
|
PDF
|
sx08a
Abstract: No abstract text available
Text: v4.0 SX-A Family FPGAs u e Le a di n g- E d ge P er f o r m a n ce • Configurable I/O Support for 3.3V/5V PCI, 5V TTL, 3.3V LVTTL, 2.5V LVCMOS2 • 2.5V, 3.3V, and 5V Mixed-Voltage Operation with 5V Input Tolerance and 5V Drive Strength • Devices Support Multiple Temperature Grades
|
Original
|
|
PDF
|
A54SX16A
Abstract: No abstract text available
Text: v4.0 SX-A Family FPGAs u e Le a di n g- E d ge P er f o r m a n ce • Configurable I/O Support for 3.3V/5V PCI, 5V TTL, 3.3V LVTTL, 2.5V LVCMOS2 • 2.5V, 3.3V, and 5V Mixed-Voltage Operation with 5V Input Tolerance and 5V Drive Strength • Devices Support Multiple Temperature Grades
|
Original
|
|
PDF
|
A54SX16A
Abstract: A54SX08 A54SX08A A54SX16 A54SX32 A54SX32A A54SX72A PAR64 REQ64 antifuse programming technology
Text: Preliminary v1.2 SX-A Family FPGAs Le a di n g- E d ge P er f o r m a n ce • Configurable I/O Support for 3.3V/5.0V PCI, 5.0V TTL, and 2.5 V/3.3V LVTTL • 2.5V, 3.3V, and 5.0V Mixed Voltage Operation with 5.0V Input Tolerance and 5.0V Drive Strength • Configurable Weak-Resistor Pull-up or Pull-down for
|
Original
|
|
PDF
|
A54SX08
Abstract: A54SX08A A54SX16 A54SX16A A54SX32 A54SX32A A54SX72A PAR64
Text: v3.0 SX-A Family FPGAs Le a di n g- E d ge P er f o r m a n ce • Configurable I/O Support for 3.3V/5.0V PCI, 5.0V TTL, and 2.5 V/3.3V LVTTL • 2.5V, 3.3V, and 5.0V Mixed Voltage Operation with 5.0V Input Tolerance and 5.0V Drive Strength • Configurable Weak-Resistor Pull-up or Pull-down for
|
Original
|
|
PDF
|
SX-APQ208
Abstract: A54SX16A
Text: v2.0 SX-A Family FPGAs Le a di n g- E d ge P er f o r m a n ce • Configurable I/O Support for 3.3V/5.0V PCI, 5.0V TTL, and 2.5 V/3.3V LVTTL • 2.5V, 3.3V, and 5.0V Mixed Voltage Operation with 5.0V Input Tolerance and 5.0V Drive Strength • Configurable Weak-Resistor Pull-up or Pull-down for
|
Original
|
|
PDF
|
SX-APQ208
Abstract: A54SX16A
Text: v2.0.1 SX-A Family FPGAs Le a di n g- E d ge P er f o r m a n ce • Configurable I/O Support for 3.3V/5.0V PCI, 5.0V TTL, and 2.5 V/3.3V LVTTL • 2.5V, 3.3V, and 5.0V Mixed Voltage Operation with 5.0V Input Tolerance and 5.0V Drive Strength • Configurable Weak-Resistor Pull-up or Pull-down for
|
Original
|
|
PDF
|
ecl 10K
Abstract: MC10H125 ttl 081 335 16 pin ttl ECL-logic
Text: ECL 10KH High-Speed Emitter-Coupled Logic Family M C 10H125 Quad ECL-to-TTL. Translator F eatu res/ Benefits PRELIMINARY INFORMATION T h is d o c u m e n t c o n ta in s spe* c if ic a t io n s and in fo r m a tio n w h ic h are s u b je c t to change. Ordering Inform ation
|
OCR Scan
|
MC10H125
10K-compatlble
MC10H125
25-pF
ecl 10K
ttl 081
335 16 pin ttl
ECL-logic
|
PDF
|
74xx151
Abstract: 74XX08 TTL 74XX04 74XX00 74xx161 74XX139 74xx04 TTL 74XX00 74XX174 74XX374
Text: National Semiconductor Application Note 319 Larry Wakeman June 1983 The MM54HC MM74HC family of high speed logic components provides a combination of speed and power characteristics that is not duplicated by bipolar logic families or any other CMOS family This CMOS family has operating
|
Original
|
MM54HC
MM74HC
54ALS
74ALS
CD4000
74xx151
74XX08
TTL 74XX04
74XX00
74xx161
74XX139
74xx04
TTL 74XX00
74XX174
74XX374
|
PDF
|
ic mm74hc
Abstract: MM74HC 74HC inverter tri-state output ic cd4000 CMOS TTL Logic Family Specifications AL 5052 CD4000 74LS SERIES cmos logic data Difference between LS, HC, HCT devices unbuffered cmos logic application note
Text: National Semiconductor Application Note 313 Larry Wakeman June 1983 The input and output characteristics of the MM54HC MM74HC high-speed CMOS logic family were conceived to meet several basic goals These goals are to provide input current and voltage requirements noise immunity and quiescent power dissipation similar to CD4000 and MM54C
|
Original
|
MM54HC
MM74HC
CD4000
MM54C
MM74C
MM54HCT
MM74HCT
MM54HC
MM74HC
ic mm74hc
74HC inverter tri-state output
ic cd4000
CMOS TTL Logic Family Specifications
AL 5052
74LS SERIES cmos logic data
Difference between LS, HC, HCT devices
unbuffered cmos logic application note
|
PDF
|
